Re: [Xen-devel] [PATCH] PL011: fix reverse logic for interrupt mask register

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

On Wed, 2013-08-21 at 15:58 +0200, Andre Przywara wrote:
> On 08/21/2013 12:04 PM, Ian Campbell wrote:
> > On Tue, 2013-08-13 at 17:12 +0200, Andre Przywara wrote:
> >> The PL011 IMSC register description is somehow fuzzy in the
> >> documentation;
> >
> > OMG pl011 docs r1p5 issue g says:
> >          On a read this register returns the current value of the mask on
> >          the relevant interrupt. On a write of 1 to the particular bit,
> >          it sets the corresponding mask of that interrupt. A write of 0
> >          clears the corresponding mask.
> >
> > Which is perfectly obvious if you read it understanding "mask an
> > interrupt" in the normal way, but in the introduction to the section on
> > interrupts it says:
> >
> >          You can enable or disable the individual interrupts by changing
> >          the mask bits in the Interrupt Mask Set/Clear Register, UARTIMSC
> >          on page 3-17. Setting the appropriate mask bit HIGH enables the
> >          interrupt.
> >
> > So IMSC is actually the "mask" of the interrupts which are enabled.
> >
> > What crappy docs!
> 
> I agree, I stumbled on this by reading IMSC and wondered how it could be 
> just 0 in the first place,

I wondered that too, but dismissed it as "mad hardware" without thinking
carefully enough!

Ian.



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