Re: [Xen-devel] [PATCH RFC 6/7] xen: arm: configure TCR_EL2 for 40 bit physical address space

[Julien Grall <julien.grall@xxxxxxxxxx>]

On 09/17/2013 02:40 AM, Ian Campbell wrote:
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Acked-by: Julien Grall <julien.grall@xxxxxxxxxx>
> ---
>  xen/arch/arm/arm64/head.S | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index 6406562..59cbcd8 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -200,12 +200,12 @@ skip_bss:
>          msr   mair_el2, x0
>  
>          /* Set up the HTCR:
> -         * PASize -- 4G
> +         * PASize -- 40 bits / 1TB
>           * Top byte is used
>           * PT walks use Outer-Shareable accesses,
>           * PT walks are write-back, write-allocate in both cache levels,
>           * Full 64-bit address space goes through this table. */
> -        ldr   x0, =0x80802500
> +        ldr   x0, =0x80822500
>          msr   tcr_el2, x0
>  
>          /* Set up the SCTLR_EL2:
> 


-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@xxxxxxxxxxxxx
http://lists.xen.org/xen-devel