[Xen-devel] [PATCH] MCHECK, AMD: Fix code to allow calls to vmce_amd_rdmsr and vmce_amd_wrmsr

[Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>]

The existing switch statement: switch ( msr & (MSR_IA32_MC0_CTL | 0x3))
causes MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3 to be wrongly routed.
The old values were:
Value                           After applying msr & (MSR_IA32_MC0_CTL | 0x3)
-------------------------------- --------------------------------------------
MSR_F10_MC4_MISC1 = 0xc0000408  0x400 : Falls to case MC0_CTL
MSR_F10_MC4_MISC2 = 0xc0000409  0x401 : Falls to case MC0_STATUS
MSR_F10_MC4_MISC3 = 0xc000040A  0x402 : Falls to case MC0_ADDR

The patch corrects the switch statement to allow vmce_amd_* functions to handle
guest's rdmsr and wrmsr calls for MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3

While at it, correct the above mentioned MSR values in msr-index.h
The values should be -
MSR_F10_MC4_MISC1 (DRAM error type) = 0x00000413
MSR_F10_MC4_MISC2 (Link error type) = 0xc0000408
MSR_F10_MC4_MISC3 (L3 cache error)  = 0xc0000409

Refer F10 BKDG F3x1[78, 70, 68, 60]. Also, MSRC0000040A does not exist from
Fam15 onwards. So let's use 0x413 for DRAM errors.

Tested on AMD Fam15 processor and works fine.

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>
---
 xen/arch/x86/cpu/mcheck/vmce.c  |    4 ++--
 xen/arch/x86/hvm/svm/svm.c      |   10 ++++++----
 xen/include/asm-x86/msr-index.h |    6 +++---
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index af3b491..448b2d7 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -107,7 +107,7 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t 
msr, uint64_t *val)
 
     *val = 0;
 
-    switch ( msr & (MSR_IA32_MC0_CTL | 3) )
+    switch ( msr ) 
     {
     case MSR_IA32_MC0_CTL:
         /* stick all 1's to MCi_CTL */
@@ -210,7 +210,7 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, 
uint64_t val)
     int ret = 1;
     unsigned int bank = (msr - MSR_IA32_MC0_CTL) / 4;
 
-    switch ( msr & (MSR_IA32_MC0_CTL | 3) )
+    switch ( msr ) 
     {
     case MSR_IA32_MC0_CTL:
         /*
diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 22a63a7..25bb792 100644
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1460,8 +1460,9 @@ static int svm_msr_read_intercept(unsigned int msr, 
uint64_t *msr_content)
         *msr_content = v->arch.hvm_svm.guest_sysenter_eip;
         break;
 
-    case MSR_IA32_MCx_MISC(4): /* Threshold register */
-    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
+    case MSR_F10_MC4_MISC1: 
+    case MSR_F10_MC4_MISC2: 
+    case MSR_F10_MC4_MISC3: 
         /*
          * MCA/MCE: We report that the threshold register is unavailable
          * for OS use (locked by the BIOS).
@@ -1659,8 +1660,9 @@ static int svm_msr_write_intercept(unsigned int msr, 
uint64_t msr_content)
         vpmu_do_wrmsr(msr, msr_content);
         break;
 
-    case MSR_IA32_MCx_MISC(4): /* Threshold register */
-    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
+    case MSR_F10_MC4_MISC1: 
+    case MSR_F10_MC4_MISC2: 
+    case MSR_F10_MC4_MISC3: 
         /*
          * MCA/MCE: Threshold register is reported to be locked, so we ignore
          * all write accesses. This behaviour matches real HW, so guests should
diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index e597a28..9904d41 100644
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -218,9 +218,9 @@
 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT        46
 
 /* AMD Family10h machine check MSRs */
-#define MSR_F10_MC4_MISC1              0xc0000408
-#define MSR_F10_MC4_MISC2              0xc0000409
-#define MSR_F10_MC4_MISC3              0xc000040A
+#define MSR_F10_MC4_MISC1              0x00000413
+#define MSR_F10_MC4_MISC2              0xc0000408
+#define MSR_F10_MC4_MISC3              0xc0000409
 
 /* AMD Family10h Bus Unit MSRs */
 #define MSR_F10_BU_CFG                 0xc0011023
-- 
1.7.9.5



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