Looking at the statistics I see that I get the expected number of
ticks per second, however I get latencies in the range [-1ms, +25us]
and the periods in the range of [3us, 1.02ms]. The upper bounds look
OK, but the lower bounds are all over the place.
Ok. Well, I'm not super expert in that area (yet), but even for the ones
that are, I think it's pretty hard to guess what could be going on
without seeing the actual code.
Is there any chance that you can share/show it? At least the relevant
chunks...
No problems, I can share the complete code it you want, there is nothing proprietary in there yet. What's the best way to do it? Put it on github? Send a tarball?
Some questions:
- "looking at the statistics", what statistics? How do you collect
them?
At every cycle I compare the current time with the expected time and calculate latency (time from when I expect the event to when it actually happens) and period.
- you say you get latencies in some range and periods in some other
range. It may be my fault, but I'm not sure I understand what you
mean with these two terms in this context, could you clarify?
Latency = difference between expected time and actual time of the event.
Period = time between two consecutive events.
This makes me think that I'm not the only thing using VIRQ_TIMER. I
seem to remember that this is called nominally every 10ms by the
Hypervisor.
Is there any way to recognize the origin of the timer?
I'm not sure if fits your exact needs, and you probably know it already,
but, just in case, have you looked at xentrace and xenalyze? There's a
blog post that could be a nice introduction to them:
I hadn't read that. I'll look at it tomorrow (it's almost midnight here).
If the exact information you're after is not among the already existing
tracepoints, it shouldn't be to hard to add one or more of those, in the
spots where you need them.
But again, it's very hard to judge without seeing the code...
I totally understand. Thanks for the effort.
Regards,
Dario
--
<<This happens because I choose it to happen!>> (Raistlin Majere)
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Senior Software Engineer, Citrix Systems R&D Ltd., Cambridge (UK)
