Re: [Xen-devel] Xen arm question

[Ian Campbell <Ian.Campbell@xxxxxxxxxx>]

On Tue, 2013-12-17 at 19:44 +0530, Mj Embd wrote:
> Hi,
> I have a trivial question, my knowledge of ARM is limited, pardon my
> ignorance. VTTBR  contains the vm id and the address of stage2 page
> table.
> AFAIK VTTBR is not banked across cores, what I mean here is the Core 0
> and Core 1 cannot see a different value of VTTBR.
> 
> If this point is valid,

It's not. Every core has it's own set of registers and coprocessors
(including mmu).

In ARM old "banked" refers to different sets of registers available on
the same core depending on what mode it is in. for example supervisor
mode and usermode have their own SPSR register, so asking for spsr will
get you a different thing depending on which mode you are in.

Ian.



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