Re: [Xen-devel] [PATCH 1/2] hvm, svm: Update AMD Thresholding MSR definitions

["Egger, Christoph" <chegger@xxxxxxxxx>]

On 15.03.08 22:50, Aravind Gopalakrishnan wrote:
> MSR 0xC000040A is marked as reserved from Fam15 onwards and
> MSR 0x413 is marked alias of MSR0xC000040A on Fam10 BKDG.
> So remove the unnecessary definition of the reserved MSR and
> use MSR_IA32_MCx_MISC() to define MSR 0x413.
> 
> Also, according to BKDG, MSR 0x413 is the first of the thresholding
> registers; MSR 0xC0000408 and MSR 0xC0000409 are second and third
> respectively. So rework the #define's accordingly.
> 
> Fam15 Model 00h-0fh  BKDG reference:
> http://support.amd.com/TechDocs/42301_15h_Mod_00h-0Fh_BKDG.pdf
> 
> Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>
> Reviewed-by: Suravee Suthikulpanit <suravee.suthikulpanit@xxxxxxx>

Reviewed-by: Christoph Egger <chegger@xxxxxxxxx>

> ---
>  xen/arch/x86/hvm/svm/svm.c      |   10 ++++++----
>  xen/include/asm-x86/msr-index.h |    6 +++---
>  2 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
> index 406d394..07c2684 100644
> --- a/xen/arch/x86/hvm/svm/svm.c
> +++ b/xen/arch/x86/hvm/svm/svm.c
> @@ -1461,8 +1461,9 @@ static int svm_msr_read_intercept(unsigned int msr, 
> uint64_t *msr_content)
>          *msr_content = v->arch.hvm_svm.guest_sysenter_eip;
>          break;
>  
> -    case MSR_IA32_MCx_MISC(4): /* Threshold register */
> -    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
> +    case MSR_F10_MC4_MISC1: /* Threshold registers */
> +    case MSR_F10_MC4_MISC2:
> +    case MSR_F10_MC4_MISC3:
>          /*
>           * MCA/MCE: We report that the threshold register is unavailable
>           * for OS use (locked by the BIOS).
> @@ -1660,8 +1661,9 @@ static int svm_msr_write_intercept(unsigned int msr, 
> uint64_t msr_content)
>          vpmu_do_wrmsr(msr, msr_content);
>          break;
>  
> -    case MSR_IA32_MCx_MISC(4): /* Threshold register */
> -    case MSR_F10_MC4_MISC1 ... MSR_F10_MC4_MISC3:
> +    case MSR_F10_MC4_MISC1: /* Threshold registers */
> +    case MSR_F10_MC4_MISC2:
> +    case MSR_F10_MC4_MISC3:
>          /*
>           * MCA/MCE: Threshold register is reported to be locked, so we ignore
>           * all write accesses. This behaviour matches real HW, so guests 
> should
> diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
> index fc9fbc6..e5ffbf2 100644
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -219,9 +219,9 @@
>  #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT      46
>  
>  /* AMD Family10h machine check MSRs */
> -#define MSR_F10_MC4_MISC1            0xc0000408
> -#define MSR_F10_MC4_MISC2            0xc0000409
> -#define MSR_F10_MC4_MISC3            0xc000040A
> +#define MSR_F10_MC4_MISC1            MSR_IA32_MCx_MISC(4)
> +#define MSR_F10_MC4_MISC2            0xc0000408
> +#define MSR_F10_MC4_MISC3            0xc0000409
>  
>  /* AMD Family10h Bus Unit MSRs */
>  #define MSR_F10_BU_CFG               0xc0011023
> 


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