[Xen-devel] [PATCH 0/3 V3] Fix AMD threshold register definitions and activate vmce_amd_* functions

[Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>]

Patch 1: Deals with correcting AMD threshold register definitions.
Patch 2: Fixes mask in vmce.c to allow vmce_amd_* functions to handle access to
         AMD thresholding registers.
Patch 3: Verify presence of AMD extended block of MISC registers before we 
decide to emulate(or not)

Changes in V2:
    - Correct time skew on the V1 patch.
Changes in V3:
    - Use #defines for the masks (per C.Egger and Boris.O comments)
    - Reword commit message
    - Rework code to care for the differences in BKDG wrt to presence of 
extended MC4 MISC registers (per Jan comments)

Aravind Gopalakrishnan (3):
  hvm,svm: Update AMD Thresholding MSR definitions
  mcheck,vmce: Allow vmce_amd_* functions to handle AMD thresolding
    MSRs
  mcheck, mce_amd: Verify presence of extended AMD_MC4_MISC registers

 xen/arch/x86/cpu/mcheck/amd_f10.c |   64 +++++++++++++++++--------------------
 xen/arch/x86/cpu/mcheck/mce_amd.h |    3 ++
 xen/arch/x86/cpu/mcheck/vmce.c    |    6 ++--
 xen/arch/x86/cpu/mcheck/vmce.h    |    3 ++
 xen/arch/x86/hvm/svm/svm.c        |   10 +++---
 xen/include/asm-x86/msr-index.h   |    6 ++--
 6 files changed, 48 insertions(+), 44 deletions(-)

-- 
1.7.9.5



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