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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [RFC PATCH v1 05/10] xen/arm: move gic definitions to seperate file
From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx> Move gic v2 register definitions to seperate file so that gic.h will hold only common definitions and helps to define gic v3 definitions. Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx> --- xen/arch/arm/gic.c | 1 + xen/arch/arm/vgic.c | 1 + xen/include/asm-arm/gic.h | 111 ------------------------------ xen/include/asm-arm/gic_v2_defs.h | 136 +++++++++++++++++++++++++++++++++++++ 4 files changed, 138 insertions(+), 111 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 973fcf9..bb718f6 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -33,6 +33,7 @@ #include <asm/domain.h> #include <asm/platform.h> +#include <asm/gic_v2_defs.h> #include <asm/gic.h> /* Access to the GIC Distributor registers through the fixmap */ diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 694a15c..9c907b5 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -28,6 +28,7 @@ #include <asm/current.h> #include "io.h" +#include <asm/gic_v2_defs.h> #include <asm/gic.h> #define REG(n) (n/4) diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index debfab8..18656fd 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -18,117 +18,6 @@ #ifndef __ASM_ARM_GIC_H__ #define __ASM_ARM_GIC_H__ -#define GICD_CTLR (0x000/4) -#define GICD_TYPER (0x004/4) -#define GICD_IIDR (0x008/4) -#define GICD_IGROUPR (0x080/4) -#define GICD_IGROUPRN (0x0FC/4) -#define GICD_ISENABLER (0x100/4) -#define GICD_ISENABLERN (0x17C/4) -#define GICD_ICENABLER (0x180/4) -#define GICD_ICENABLERN (0x1fC/4) -#define GICD_ISPENDR (0x200/4) -#define GICD_ISPENDRN (0x27C/4) -#define GICD_ICPENDR (0x280/4) -#define GICD_ICPENDRN (0x2FC/4) -#define GICD_ISACTIVER (0x300/4) -#define GICD_ISACTIVERN (0x37C/4) -#define GICD_ICACTIVER (0x380/4) -#define GICD_ICACTIVERN (0x3FC/4) -#define GICD_IPRIORITYR (0x400/4) -#define GICD_IPRIORITYRN (0x7F8/4) -#define GICD_ITARGETSR (0x800/4) -#define GICD_ITARGETSRN (0xBF8/4) -#define GICD_ICFGR (0xC00/4) -#define GICD_ICFGRN (0xCFC/4) -#define GICD_NSACR (0xE00/4) -#define GICD_NSACRN (0xEFC/4) -#define GICD_SGIR (0xF00/4) -#define GICD_CPENDSGIR (0xF10/4) -#define GICD_CPENDSGIRN (0xF1C/4) -#define GICD_SPENDSGIR (0xF20/4) -#define GICD_SPENDSGIRN (0xF2C/4) -#define GICD_ICPIDR2 (0xFE8/4) - -#define GICD_SGI_TARGET_LIST_SHIFT (24) -#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT) -#define GICD_SGI_TARGET_LIST (0UL<<GICD_SGI_TARGET_LIST_SHIFT) -#define GICD_SGI_TARGET_OTHERS (1UL<<GICD_SGI_TARGET_LIST_SHIFT) -#define GICD_SGI_TARGET_SELF (2UL<<GICD_SGI_TARGET_LIST_SHIFT) -#define GICD_SGI_TARGET_SHIFT (16) -#define GICD_SGI_TARGET_MASK (0xFFUL<<GICD_SGI_TARGET_SHIFT) -#define GICD_SGI_GROUP1 (1UL<<15) -#define GICD_SGI_INTID_MASK (0xFUL) - -#define GICC_CTLR (0x0000/4) -#define GICC_PMR (0x0004/4) -#define GICC_BPR (0x0008/4) -#define GICC_IAR (0x000C/4) -#define GICC_EOIR (0x0010/4) -#define GICC_RPR (0x0014/4) -#define GICC_HPPIR (0x0018/4) -#define GICC_APR (0x00D0/4) -#define GICC_NSAPR (0x00E0/4) -#define GICC_DIR (0x1000/4) - -#define GICH_HCR (0x00/4) -#define GICH_VTR (0x04/4) -#define GICH_VMCR (0x08/4) -#define GICH_MISR (0x10/4) -#define GICH_EISR0 (0x20/4) -#define GICH_EISR1 (0x24/4) -#define GICH_ELSR0 (0x30/4) -#define GICH_ELSR1 (0x34/4) -#define GICH_APR (0xF0/4) -#define GICH_LR (0x100/4) - -/* Register bits */ -#define GICD_CTL_ENABLE 0x1 - -#define GICD_TYPE_LINES 0x01f -#define GICD_TYPE_CPUS 0x0e0 -#define GICD_TYPE_SEC 0x400 - -#define GICC_CTL_ENABLE 0x1 -#define GICC_CTL_EOI (0x1 << 9) - -#define GICC_IA_IRQ 0x03ff -#define GICC_IA_CPU_MASK 0x1c00 -#define GICC_IA_CPU_SHIFT 10 - -#define GICH_HCR_EN (1 << 0) -#define GICH_HCR_UIE (1 << 1) -#define GICH_HCR_LRENPIE (1 << 2) -#define GICH_HCR_NPIE (1 << 3) -#define GICH_HCR_VGRP0EIE (1 << 4) -#define GICH_HCR_VGRP0DIE (1 << 5) -#define GICH_HCR_VGRP1EIE (1 << 6) -#define GICH_HCR_VGRP1DIE (1 << 7) - -#define GICH_MISR_EOI (1 << 0) -#define GICH_MISR_U (1 << 1) -#define GICH_MISR_LRENP (1 << 2) -#define GICH_MISR_NP (1 << 3) -#define GICH_MISR_VGRP0E (1 << 4) -#define GICH_MISR_VGRP0D (1 << 5) -#define GICH_MISR_VGRP1E (1 << 6) -#define GICH_MISR_VGRP1D (1 << 7) - -#define GICH_LR_VIRTUAL_MASK 0x3ff -#define GICH_LR_VIRTUAL_SHIFT 0 -#define GICH_LR_PHYSICAL_MASK 0x3ff -#define GICH_LR_PHYSICAL_SHIFT 10 -#define GICH_LR_STATE_MASK 0x3 -#define GICH_LR_STATE_SHIFT 28 -#define GICH_LR_PRIORITY_SHIFT 23 -#define GICH_LR_MAINTENANCE_IRQ (1<<19) -#define GICH_LR_PENDING (1<<28) -#define GICH_LR_ACTIVE (1<<29) -#define GICH_LR_GRP1 (1<<30) -#define GICH_LR_HW (1<<31) -#define GICH_LR_CPUID_SHIFT 9 -#define GICH_VTR_NRLRGS 0x3f - /* * The minimum GICC_BPR is required to be in the range 0-3. We set * GICC_BPR to 0 but we must expect that it might be 3. This means we diff --git a/xen/include/asm-arm/gic_v2_defs.h b/xen/include/asm-arm/gic_v2_defs.h new file mode 100644 index 0000000..2366685 --- /dev/null +++ b/xen/include/asm-arm/gic_v2_defs.h @@ -0,0 +1,136 @@ +/* + * ARM Generic Interrupt Controller support + * + * Tim Deegan <tim@xxxxxxx> + * Copyright (c) 2011 Citrix Systems. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define GICD_CTLR (0x000/4) +#define GICD_TYPER (0x004/4) +#define GICD_IIDR (0x008/4) +#define GICD_IGROUPR (0x080/4) +#define GICD_IGROUPRN (0x0FC/4) +#define GICD_ISENABLER (0x100/4) +#define GICD_ISENABLERN (0x17C/4) +#define GICD_ICENABLER (0x180/4) +#define GICD_ICENABLERN (0x1fC/4) +#define GICD_ISPENDR (0x200/4) +#define GICD_ISPENDRN (0x27C/4) +#define GICD_ICPENDR (0x280/4) +#define GICD_ICPENDRN (0x2FC/4) +#define GICD_ISACTIVER (0x300/4) +#define GICD_ISACTIVERN (0x37C/4) +#define GICD_ICACTIVER (0x380/4) +#define GICD_ICACTIVERN (0x3FC/4) +#define GICD_IPRIORITYR (0x400/4) +#define GICD_IPRIORITYRN (0x7F8/4) +#define GICD_ITARGETSR (0x800/4) +#define GICD_ITARGETSRN (0xBF8/4) +#define GICD_ICFGR (0xC00/4) +#define GICD_ICFGRN (0xCFC/4) +#define GICD_NSACR (0xE00/4) +#define GICD_NSACRN (0xEFC/4) +#define GICD_SGIR (0xF00/4) +#define GICD_CPENDSGIR (0xF10/4) +#define GICD_CPENDSGIRN (0xF1C/4) +#define GICD_SPENDSGIR (0xF20/4) +#define GICD_SPENDSGIRN (0xF2C/4) +#define GICD_ICPIDR2 (0xFE8/4) + +#define GICD_SGI_TARGET_LIST_SHIFT (24) +#define GICD_SGI_TARGET_LIST_MASK (0x3UL << GICD_SGI_TARGET_LIST_SHIFT) +#define GICD_SGI_TARGET_LIST (0UL<<GICD_SGI_TARGET_LIST_SHIFT) +#define GICD_SGI_TARGET_OTHERS (1UL<<GICD_SGI_TARGET_LIST_SHIFT) +#define GICD_SGI_TARGET_SELF (2UL<<GICD_SGI_TARGET_LIST_SHIFT) +#define GICD_SGI_TARGET_SHIFT (16) +#define GICD_SGI_TARGET_MASK (0xFFUL<<GICD_SGI_TARGET_SHIFT) +#define GICD_SGI_GROUP1 (1UL<<15) +#define GICD_SGI_INTID_MASK (0xFUL) + +#define GICC_CTLR (0x0000/4) +#define GICC_PMR (0x0004/4) +#define GICC_BPR (0x0008/4) +#define GICC_IAR (0x000C/4) +#define GICC_EOIR (0x0010/4) +#define GICC_RPR (0x0014/4) +#define GICC_HPPIR (0x0018/4) +#define GICC_APR (0x00D0/4) +#define GICC_NSAPR (0x00E0/4) +#define GICC_DIR (0x1000/4) + +#define GICH_HCR (0x00/4) +#define GICH_VTR (0x04/4) +#define GICH_VMCR (0x08/4) +#define GICH_MISR (0x10/4) +#define GICH_EISR0 (0x20/4) +#define GICH_EISR1 (0x24/4) +#define GICH_ELSR0 (0x30/4) +#define GICH_ELSR1 (0x34/4) +#define GICH_APR (0xF0/4) +#define GICH_LR (0x100/4) + +/* Register bits */ +#define GICD_CTL_ENABLE 0x1 + +#define GICD_TYPE_LINES 0x01f +#define GICD_TYPE_CPUS 0x0e0 +#define GICD_TYPE_SEC 0x400 + +#define GICC_CTL_ENABLE 0x1 +#define GICC_CTL_EOI (0x1 << 9) + +#define GICC_IA_IRQ 0x03ff +#define GICC_IA_CPU_MASK 0x1c00 +#define GICC_IA_CPU_SHIFT 10 + +#define GICH_HCR_EN (1 << 0) +#define GICH_HCR_UIE (1 << 1) +#define GICH_HCR_LRENPIE (1 << 2) +#define GICH_HCR_NPIE (1 << 3) +#define GICH_HCR_VGRP0EIE (1 << 4) +#define GICH_HCR_VGRP0DIE (1 << 5) +#define GICH_HCR_VGRP1EIE (1 << 6) +#define GICH_HCR_VGRP1DIE (1 << 7) + +#define GICH_MISR_EOI (1 << 0) +#define GICH_MISR_U (1 << 1) +#define GICH_MISR_LRENP (1 << 2) +#define GICH_MISR_NP (1 << 3) +#define GICH_MISR_VGRP0E (1 << 4) +#define GICH_MISR_VGRP0D (1 << 5) +#define GICH_MISR_VGRP1E (1 << 6) +#define GICH_MISR_VGRP1D (1 << 7) + +#define GICH_LR_VIRTUAL_MASK 0x3ff +#define GICH_LR_VIRTUAL_SHIFT 0 +#define GICH_LR_PHYSICAL_MASK 0x3ff +#define GICH_LR_PHYSICAL_SHIFT 10 +#define GICH_LR_STATE_MASK 0x3 +#define GICH_LR_STATE_SHIFT 28 +#define GICH_LR_PRIORITY_SHIFT 23 +#define GICH_LR_MAINTENANCE_IRQ (1<<19) +#define GICH_LR_PENDING (1<<28) +#define GICH_LR_ACTIVE (1<<29) +#define GICH_LR_GRP1 (1<<30) +#define GICH_LR_HW (1<<31) +#define GICH_LR_CPUID_SHIFT 9 +#define GICH_VTR_NRLRGS 0x3f + +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ -- 1.7.9.5 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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