Re: [Xen-devel] Fwd: [PATCH RFC 3/4] x86/AMD: support further feature masking MSRs

[Aravind Gopalakrishnan <aravind.gopalakrishnan@xxxxxxx>]

On 4/1/2014 6:10 PM, Aravind Gopalakrishnan wrote:
> > Newer AMD CPUs also allow masking CPUID leaf 6 ECX and CPUID leaf 7
> > sub-leaf 0 EAX and EBX.
> >
> > Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx 
> > <mailto:jbeulich@xxxxxxxx>>
> > TBD:
> > - Fam15M0x is documented to not have MSR C0011002 despite 
> > CPUID[7,0].EBX != 0 from model 02
> >   onwards, and contrary to what I see on the system I have access to 
> > (which is model 02)
> > - Fam12, Fam14, and Fam16 are documented to not have MSR C0011003 
> > despite CPUID[6].ECX != 0
> Fam10 too has cpuid[6].ecx != 0 but no MSR C0011003
>
> > - Fam11 is documented to not even have MSR C0011004 and C0011005
> I am still trying to get some clarity on this;
Here's more info regarding your questions:
1. This is a documentation error.
2. We cannot mask cpuid[6].ecx on any of these families: 0x10, 0x11, 
0x12,0x14,0x16 as feature is not supported..
3. We cannot mask standard,extended cpuid feature bits on Fam0x11 as 
feature is not supported.
So simple enough additions to your patch to include some family checks:

+    if (c->cpuid_level >= 7)
+        cpuid_count(7, 0, &eax, &ebx, &ecx, &edx);
+    else
+        ebx = eax = 0;
+    if ((eax | ebx) && ~(l7s0_eax & l7s0_ebx) &&
+         c->x86 == 0x15 && c->x86_model >= 0x2) {
+        if (l7s0_eax > eax)
+            l7s0_eax = eax;
+            l7s0_ebx &= ebx;
+            printk("Writing CPUID leaf 7 subleaf 0 feature mask EAX:EBX 
-> %08Xh:%08Xh\n",
+                   l7s0_eax, l7s0_ebx);
+    } else
+          skip_l7s0_eax_ebx = 1;
+    ecx = c->cpuid_level >= 6 ? cpuid_ecx(6) : 0;
+    if (ecx && ~thermal_ecx && c->x86 == 0x15) {
+        thermal_ecx &= ecx;
+        printk("Writing CPUID thermal/power feature mask ECX -> %08Xh\n",
+                thermal_ecx);
+    } else
+        skip_thermal_ecx = 1;
  setmask:
-   /* FIXME check if processor supports CPUID masking */
    /* AMD processors prior to family 10h required a 32-bit password */
-   if (c->x86 >= 0x10) {
+   if (c->x86 >= 0x10 && c->x86 != 0x11) {
        wrmsr(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
        wrmsr(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);
+        if (!skip_l7s0_eax_ebx)
+            wrmsr(MSR_AMD_L7S0_FEATURE_MASK, l7s0_ebx, l7s0_eax);
+        if (!skip_thermal_ecx) {
+            rdmsr(MSR_AMD_THRM_FEATURE_MASK, eax, edx);
+            wrmsr(MSR_AMD_THRM_FEATURE_MASK, thermal_ecx, edx);
+        }
    } else {
        wrmsr_amd(MSR_K8_FEATURE_MASK, feat_edx, feat_ecx);
        wrmsr_amd(MSR_K8_EXT_FEATURE_MASK, extfeat_edx, extfeat_ecx);

Tested on a fam16h system with "cpuid_mask_thermal_ecx=0x0 
cpuid_mask_l7s0_ebx=0x0" boot args and works fine.
Thanks,
-Aravind.


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