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Re: [Xen-devel] [PATCH v2 2/3] x86/AMD: support further feature masking MSRs

On 04/08/2014 10:33 AM, Jan Beulich wrote:
On 08.04.14 at 16:14, <boris.ostrovsky@xxxxxxxxxx> wrote:
On 04/08/2014 10:02 AM, Jan Beulich wrote:
On 08.04.14 at 15:50, <boris.ostrovsky@xxxxxxxxxx> wrote:
On 04/08/2014 03:15 AM, Jan Beulich wrote:
On 07.04.14 at 17:21, <boris.ostrovsky@xxxxxxxxxx> wrote:
On 04/07/2014 05:43 AM, Jan Beulich wrote:

@@ -179,11 +196,39 @@ static void __devinit set_cpuidmask(cons
        printk("Writing CPUID extended feature mask ECX:EDX -> %08Xh:%08Xh\n",
               extfeat_ecx, extfeat_edx);
+ if (c->cpuid_level >= 7)
+               cpuid_count(7, 0, &eax, &ebx, &ecx, &edx);
+       else
+               ebx = eax = 0;
+       if ((eax | ebx) && ~(l7s0_eax & l7s0_ebx)) {
+               if (l7s0_eax > eax)
+                       l7s0_eax = eax;
+               l7s0_ebx &= ebx;

Can you explain why eax is treated differently here (i.e. not ANDing it
as is done with ebx)?
Generally I think code like this implies that you know the specification:
eax here represents the maximum supported subleaf, and hence
needs to be limited rather than masked.
All specs that I have say that bits of CPUID Fn0000_0007_EAX_x0 are
Intel's SDM Vol 2 rev 49 (325383-049US) says "07H Sub-leaf 0 (Input
ECX = 0). EAX Bits 31-00: Reports the maximum input value for
supported leaf 7 sub-leaves." Not sure what other specs you might
be looking at.
This is a patch to xen/arch/x86/cpu/amd.c so I was looking at AMD's
BKDGs.  Why is Intel's definition relevant here?
Because leaf 7 is (largely) Intel-defined (AMD adds their extensions
usually at leaves 800000xx).

I don't know whether we can assume that AMD will follow the same definitions. They usually try not to deliberately do something differently there but this is never guaranteed.


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