[Xen-devel] [xen-unstable test] 25960: regressions - FAIL

[xen.org <Ian.Jackson@xxxxxxxxxxxxx>]

flight 25960 xen-unstable real [real]
http://www.chiark.greenend.org.uk/~xensrcts/logs/25960/

Regressions :-(

Tests which did not succeed and are blocking,
including tests which could not be run:
 test-amd64-i386-xl-qemuu-win7-amd64  7 windows-install    fail REGR. vs. 25954

Regressions which are regarded as allowable (not blocking):
 test-amd64-amd64-xl-sedf     11 guest-saverestore         fail REGR. vs. 25954

Tests which did not succeed, but are not blocking:
 test-armhf-armhf-xl          10 migrate-support-check        fail   never pass
 test-amd64-amd64-xl-pcipt-intel  9 guest-start                 fail never pass
 test-amd64-i386-xl-qemut-winxpsp3 14 guest-stop                fail never pass
 test-amd64-i386-xl-qemuu-winxpsp3 14 guest-stop                fail never pass
 test-amd64-i386-xl-qemut-winxpsp3-vcpus1 14 guest-stop         fail never pass
 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1 14 guest-stop         fail never pass
 test-amd64-amd64-xl-win7-amd64 14 guest-stop                   fail never pass
 test-amd64-amd64-xl-qemuu-win7-amd64 14 guest-stop             fail never pass
 test-amd64-i386-xl-win7-amd64 14 guest-stop                   fail  never pass
 test-amd64-i386-xl-qemut-win7-amd64 14 guest-stop              fail never pass
 test-amd64-amd64-xl-qemut-winxpsp3 14 guest-stop               fail never pass
 test-amd64-amd64-xl-winxpsp3 14 guest-stop                   fail   never pass
 test-amd64-i386-xl-winxpsp3-vcpus1 14 guest-stop               fail never pass
 test-amd64-i386-xl-winxpsp3  14 guest-stop                   fail   never pass
 test-amd64-amd64-xl-qemut-win7-amd64 14 guest-stop             fail never pass
 test-amd64-amd64-xl-qemuu-winxpsp3 14 guest-stop               fail never pass

version targeted for testing:
 xen                  0b182202fef8ebfc093a00ead9414a683eb8807c
baseline version:
 xen                  8cfc8e520679e029bed51ccc2540a136fc0fbd9b

------------------------------------------------------------
People who touched revisions under test:
  Ian Campbell <ian.campbell@xxxxxxxxxx>
  Julien Grall <julien.grall@xxxxxxxxxx>
------------------------------------------------------------

jobs:
 build-amd64                                                  pass    
 build-armhf                                                  pass    
 build-i386                                                   pass    
 build-amd64-oldkern                                          pass    
 build-i386-oldkern                                           pass    
 build-amd64-pvops                                            pass    
 build-armhf-pvops                                            pass    
 build-i386-pvops                                             pass    
 test-amd64-amd64-xl                                          pass    
 test-armhf-armhf-xl                                          pass    
 test-amd64-i386-xl                                           pass    
 test-amd64-i386-rhel6hvm-amd                                 pass    
 test-amd64-i386-qemut-rhel6hvm-amd                           pass    
 test-amd64-i386-qemuu-rhel6hvm-amd                           pass    
 test-amd64-i386-freebsd10-amd64                              pass    
 test-amd64-amd64-xl-qemuu-ovmf-amd64                         pass    
 test-amd64-i386-xl-qemuu-ovmf-amd64                          pass    
 test-amd64-amd64-xl-qemut-win7-amd64                         fail    
 test-amd64-i386-xl-qemut-win7-amd64                          fail    
 test-amd64-amd64-xl-qemuu-win7-amd64                         fail    
 test-amd64-i386-xl-qemuu-win7-amd64                          fail    
 test-amd64-amd64-xl-win7-amd64                               fail    
 test-amd64-i386-xl-win7-amd64                                fail    
 test-amd64-i386-xl-credit2                                   pass    
 test-amd64-i386-freebsd10-i386                               pass    
 test-amd64-amd64-xl-pcipt-intel                              fail    
 test-amd64-i386-rhel6hvm-intel                               pass    
 test-amd64-i386-qemut-rhel6hvm-intel                         pass    
 test-amd64-i386-qemuu-rhel6hvm-intel                         pass    
 test-amd64-i386-xl-multivcpu                                 pass    
 test-amd64-amd64-pair                                        pass    
 test-amd64-i386-pair                                         pass    
 test-amd64-amd64-xl-sedf-pin                                 pass    
 test-amd64-amd64-xl-sedf                                     fail    
 test-amd64-i386-xl-qemut-winxpsp3-vcpus1                     fail    
 test-amd64-i386-xl-qemuu-winxpsp3-vcpus1                     fail    
 test-amd64-i386-xl-winxpsp3-vcpus1                           fail    
 test-amd64-amd64-xl-qemut-winxpsp3                           fail    
 test-amd64-i386-xl-qemut-winxpsp3                            fail    
 test-amd64-amd64-xl-qemuu-winxpsp3                           fail    
 test-amd64-i386-xl-qemuu-winxpsp3                            fail    
 test-amd64-amd64-xl-winxpsp3                                 fail    
 test-amd64-i386-xl-winxpsp3                                  fail    


------------------------------------------------------------
sg-report-flight on osstest.cam.xci-test.com
logs: /home/xc_osstest/logs
images: /home/xc_osstest/images

Logs, config files, etc. are available at
    http://www.chiark.greenend.org.uk/~xensrcts/logs

Test harness code can be found at
    http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary


Not pushing.

------------------------------------------------------------
commit 0b182202fef8ebfc093a00ead9414a683eb8807c
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Tue Apr 15 14:06:42 2014 +0100

    xen/arm: Don't let guess access to Debug and Performance Monitor registers
    
    Debug and performance registers are not properly switched by Xen.
    
    Trap them and inject an undefined instruction, except for those registers
    which might be unconditionally accessed which we implement as RAZ/WI.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

commit a0453db0c6ead85e0e2143c133268bcc5a017f73
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Tue Apr 15 12:45:28 2014 +0100

    xen/arm: Don't expose implementation defined registers (Cp15 c15) to the 
guest
    
    On Cortex-A15, CP15 c15 contains registers to retrieve data from L1/L2 RAM.
    
    Exposing this registers to guest may result to leak data from Xen and/or
    another guest.
    
    By default trap every registers and inject an undefined instruction.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

commit 11faafd9d9739a47d5fa360a43669f52672ef40e
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Mon Apr 14 20:00:14 2014 +0100

    xen/arm: Trap cache and TCM lockdown registers
    
    Some cp15 c9/c10/c11 encodings are used for:
         - cache control
         - TCM control
         - branch predictor control
    
    All of them are implementation defined. For now inject an undefined 
exception
    if the guest wants try to access it.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

commit cda12fa0cee7023878598ff8ced3613b57576ce3
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Mon Apr 14 20:46:43 2014 +0100

    xen/arm: Upgrade DCISW into DCCISW
    
    A guest is allowed to use invalidate cache by set/way instruction (i.e 
DCISW)
    without any restriction. As the cache is shared with Xen, the guest 
invalidate
    an address being in used by Xen. This may lead a Xen crash because the 
memory
    state is invalid.
    Set the bit HCR.SWIO to upgrade invalidate cache by set/way instruction to 
an
    invalidate and clean.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Reported-by: Thomas Leonard <tal36@xxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

commit 5496c642535da9c5738a3e19276de564304a5082
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Mon Apr 14 20:37:16 2014 +0100

    xen/arm: Don't let the guest access the coprocessors registers
    
    In Xen we only handle save/restore for coprocessor 10 and 11 (NEON). Other
    coprocessors (0-9, 12-13) are currently exposed to the guest and may lead
    to data shared between guest.
    
    Disable access to all coprocessor except 10 and 11 by setting correctly
    HCTPR.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>

commit 60f737636c2be52fe1af2f1a3a2f66acacdc6a30
Author: Julien Grall <julien.grall@xxxxxxxxxx>
Date:   Mon Apr 14 19:01:20 2014 +0100

    xen/arm: Inject an undefined instruction when the coproc/sysreg is not 
handled
    
    Currently Xen panics if it's unable to handle a coprocessor/sysreg 
instruction.
    Replace this behavior by inject an undefined instruction to the faulty guest
    and log if Xen is in debug mode.
    
    This is CVE-2014-2915 / XSA-93.
    
    Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
    Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
(qemu changes not included)

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