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[Xen-devel] [PATCH] xen/arm64: disable alignment check

Alignment check is enabled by default at Xen boot. This leads to:

(XEN) Hypervisor Trap. HSR=0x96000021 EC=0x25 IL=1 Syndrome=21
(XEN) CPU0: Unexpected Trap: Hypervisor
(XEN) ----[ Xen-4.4.0  arm64  debug=n  Not tainted ]----
(XEN) CPU:    0
(XEN) PC:     000000000020a0e8 evtchn_fifo_init+0x3c/0x88
(XEN) LR:     00000000002096b4
(XEN) SP:     000080007fddfd20
(XEN) CPSR:   00000349 MODE:64-bit EL2h (Hypervisor, handler)
(XEN)      X0: 0000000000000000  X1: 000080000800a060  X2: 000000000000000c
(XEN)      X3: 000080003dce5000  X4: 000080000800b000  X5: 0000000000000060
(XEN)      X6: 000080000800a000  X7: ffffffffffffffff  X8: 000000000000001d
(XEN)      X9: 1999999999999999 X10: 0101010101010101 X11: 0000000000000020
(XEN)     X12: 0000000000000007 X13: 0000000000000080 X14: 0000000000000000
(XEN)     X15: 0000007fa3b5e598 X16: 0000000000000020 X17: 0000007fa3b90420
(XEN)     X18: 0000007fdc8e50b0 X19: 000080000800b000 X20: ffffffc01cf5fdd0
(XEN)     X21: 000080007fddfdb8 X22: 00000000002dd000 X23: 000080000800b000
(XEN)     X24: 000080000800b000 X25: 0000000000000003 X26: 000080000800b0b8
(XEN)     X27: 000080000800a020 X28: 000080000800a060  FP: ffffffc01cf5fda0
(XEN)   VTCR_EL2: 80022558
(XEN)  VTTBR_EL2: 0001000088014000
(XEN)  SCTLR_EL2: 30cd183f
(XEN)    HCR_EL2: 0000000080282835
(XEN)  TTBR0_EL2: 00000000ffeca000
(XEN)    ESR_EL2: 96000021
(XEN)  HPFAR_EL2: 0000000000000000
(XEN)    FAR_EL2: 000080003dce500c
(XEN) Xen stack trace from sp=000080007fddfd20:
(XEN)    0000000000000001 00000000002096b4 000080007fddfdb8 0000000000208ae8
(XEN)    000080007fddfeb0 000080007fddfeb0 ffffffffffffffff ffffffc000093578
(XEN)    0000000080000145 0000000000000015 0000000000000114 000000000000001d
(XEN)    ffffffc00061f000 ffffffc01cf5c000 000000000023e3f0 000080007fd32000
(XEN)    000000064cbe0760 00000000002dd938 000000000021e000 000000011dcd0000
(XEN)    000000001d966440 00000000002a0800 000000005a000ea1 000000000023f1f0
(XEN)    00000000002d8458 00000000002a3b00 0000000000084501 ffffffc01c045540
(XEN)    ffffffffffffffff ffffffc000093578 0000000080000145 0000000000000015
(XEN)    0000000000000114 000000000000001d ffffffc00061f000 ffffffc01cf5c000
(XEN)    0000000000241acc 0000000000000000 ffffffc01d96a8e8 ffffffc01cf67da0
(XEN)    00000000000004bc 0000000000000007 0000000000239a24 0000000000000000
(XEN)    000000000023f47c 0000000000000100 0000800008010f30 0000000000000100
(XEN)    ffffffc01cf5c000 0000000000241b84 0000000000000000 ffffffc01cf5fdd0
(XEN)    0000000000000001 0000000100000000 0000007fdc8e5328 0000000000004000
(XEN)    0000000000000000 ffffffffffffffff 000000000000001d 1999999999999999
(XEN)    0101010101010101 0000000000000020 0000000000000007 0000000000000080
(XEN)    0000000000000000 0000007fa3b5e598 0000000000000020 0000007fa3b90420
(XEN)    0000007fdc8e50b0 0000000000084501 ffffffc01c045540 0000007fdc8e5320
(XEN)    ffffffc01df35858 0000007fdc8e5320 0000000000000015 0000000000000114
(XEN)    000000000000001d ffffffc00061f000 ffffffc01cf5c000 ffffffc01cf5fda0
(XEN)    ffffffc0002b7a8c ffffffffffffffff ffffffc000093578 0000000080000145
(XEN)    0000000080000000 0000000000000000 0000000000000000 0000007fdc8e5310
(XEN)    ffffffc01cf5fda0 0000007fa3abf1fc cfdfdfdfdfdfdfcf cfdfdfdfdfdfdfcf
(XEN) Xen call trace:
(XEN)    [<000000000020a0e8>] evtchn_fifo_init+0x3c/0x88 (PC)
(XEN)    [<00000000002096b4>] do_event_channel_op+0xd6c/0xe54 (LR)

Faulting instruction is:
20a0e8: f8626860    ldr x0, [x3,x2]

Disabling alignment check has no effect on exclusive load/store instructions.
 xen/arch/arm/arm64/head.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 31afdd0..0599bf9 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -239,9 +239,9 @@ skip_bss:
          * Write-implies-XN disabled (for now),
          * D-cache disabled (for now),
          * I-cache enabled,
-         * Alignment checking enabled,
+         * Alignment checking disabled,
          * MMU translation disabled (for now). */
-        ldr   x0, =(HSCTLR_BASE|SCTLR_A)
+        ldr   x0, =(HSCTLR_BASE)
         msr   SCTLR_EL2, x0
         /* Rebuild the boot pagetable's first-level entries. The structure

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