Re: [Xen-devel] [PATCH v5 20/21] xen/arm: add SGI handling for GICv3

[Stefano Stabellini <stefano.stabellini@xxxxxxxxxxxxx>]

On Thu, 12 Jun 2014, vijay.kilari@xxxxxxxxx wrote:
> +static int vgicv3_to_sgi(struct vcpu *v, register_t sgir)
> +{
> +    int virq;
> +    int irqmode;
> +    enum gic_sgi_mode sgi_mode;
> +    unsigned long vcpu_mask = 0;
> +
> +    irqmode = (sgir >> ICH_SGI_IRQMODE_SHIFT) & ICH_SGI_IRQMODE_MASK;
> +    virq = (sgir >> ICH_SGI_IRQ_SHIFT ) & ICH_SGI_IRQ_MASK;
> +    vcpu_mask = sgir & ICH_SGI_TARGETLIST_MASK;
> +
> +    /* Map GIC sgi value to enum value */
> +    switch ( irqmode )
> +    {
> +    case ICH_SGI_TARGET_LIST:
> +        sgi_mode = SGI_TARGET_LIST;
> +        break;
> +    case ICH_SGI_TARGET_OTHERS:
> +        sgi_mode = SGI_TARGET_OTHERS;
> +        break;
> +    default:
> +        BUG();

If this field can be written by the guest than a BUG is a mistake (a
guest could crash the hypervisor).


> +    }
> +
> +    return vgic_to_sgi(v, sgir, sgi_mode, virq, vcpu_mask);
> +}
> +
> +int vgic_emulate(struct cpu_user_regs *regs, union hsr hsr)
> +{
> +    struct vcpu *v = current;
> +    struct hsr_sysreg sysreg = hsr.sysreg;
> +    register_t *r = select_user_reg(regs, sysreg.reg);
> +
> +    ASSERT (hsr.ec == HSR_EC_SYSREG);
> +
> +    switch ( hsr.bits & HSR_SYSREG_REGS_MASK )
> +    {
> +    case HSR_SYSREG_ICC_SGI1R_EL1:
> +        /* WO */
> +        if ( !sysreg.read )
> +            return vgicv3_to_sgi(v, *r);
> +        else
> +        {
> +            gdprintk(XENLOG_WARNING, "Reading SGI1R_EL1 - WO register\n");
> +            return 0;
> +        }
> +    default:
> +        return 0;
> +    }
> +}
> +
>  static const struct mmio_handler_ops vgic_rdistr_mmio_handler = {
>      .read_handler  = vgic_v3_rdistr_mmio_read,
>      .write_handler = vgic_v3_rdistr_mmio_write,

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