[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] Bisected Xen-unstable: "Segment register inaccessible for d1v0" when starting HVM guest on intel
Hi, On intel machines when starting a HVM guest with qemu upstream i get: (d2) [2014-06-27 20:07:46] Booting from Hard Disk... (d2) [2014-06-27 20:07:46] Booting from 0000:7c00 (XEN) [2014-06-27 20:08:00] irq.c:380: Dom1 callback via changed to Direct Vector 0xf3 (XEN) [2014-06-27 20:08:00] irq.c:380: Dom2 callback via changed to Direct Vector 0xf3 (XEN) [2014-06-27 20:08:03] Segment register inaccessible for d1v0 (XEN) [2014-06-27 20:08:03] (If you see this outside of debugging activity, please report to xen-devel@xxxxxxxxxxxxxxxxxxxx) Bisecting turned out pointing to: 58658992c16e330b89c0403bd5c3f68f8926419d is the first bad commit commit 58658992c16e330b89c0403bd5c3f68f8926419d Author: Feng Wu <feng.wu@xxxxxxxxx> Date: Mon May 12 17:04:50 2014 +0200 x86/hvm: add SMAP support to HVM guest Intel new CPU supports SMAP (Supervisor Mode Access Prevention). SMAP prevents supervisor-mode accesses to any linear address with a valid translation for which the U/S flag (bit 2) is 1 in every paging-structure entry controlling the translation for the linear address. This is on a intel NUC (core i5) using xen-unstable. cpuinfo: processor : 0 vendor_id : GenuineIntel cpu family : 6 model : 58 model name : Intel(R) Core(TM) i5-3427U CPU @ 1.80GHz stepping : 9 microcode : 0x19 cpu MHz : 2294.840 cache size : 3072 KB physical id : 0 siblings : 4 core id : 0 cpu cores : 2 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 13 wp : yes flags : fpu de tsc msr pae mce cx8 apic sep mca cmov pat clflush acpi mmx fxsr sse sse2 ss ht syscall nx lm constant_tsc rep_good nopl nonstop_tsc eagerfpu pni pclmulqdq monitor est ssse3 cx16 sse4_1 sse4_2 popcnt tsc_deadline_timer aes xsave avx f16c rdrand hypervisor lahf_lm ida arat epb xsaveopt pln pts dtherm fsgsbase erms bogomips : 4589.68 clflush size : 64 cache_alignment : 64 address sizes : 36 bits physical, 48 bits virtual power management: -- Sander _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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