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Re: [Xen-devel] [RFC v2 PATCH] xen/arm: Deliver interrupts to vcpu specified in IROUTER



On Sat, Sep 13, 2014 at 12:12 AM, Stefano Stabellini
<stefano.stabellini@xxxxxxxxxxxxx> wrote:
> On Fri, 12 Sep 2014, vijay.kilari@xxxxxxxxx wrote:
>> From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
>>
>> In GICv3 use IROUTER register contents to deliver irq to
>> specified vcpu.
>>
>> vgic irouter[irq] is used to represent vcpu number for which
>> irq affinity is assigned. Bit[31] is used to store IROUTER
>> bit[31] value to represent irq mode.
>>
>> This patch is similar to Stefano's commit
>> 5b3a817ea33b891caf7d7d788da9ce6deffa82a1 for GICv2
>>
>> @@ -948,24 +1016,25 @@ static int vgic_v3_get_irq_priority(struct vcpu *v, 
>> unsigned int irq)
>>  static int vgic_v3_vcpu_init(struct vcpu *v)
>>  {
>>      int i;
>> -    uint64_t affinity;
>>
>>      /* For SGI and PPI the target is always this CPU */
>> -    affinity = (MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 3) << 32 |
>> -                MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 2) << 16 |
>> -                MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 1) << 8  |
>> -                MPIDR_AFFINITY_LEVEL(v->arch.vmpidr, 0));
>> -
>> +    /* XXX: Store vcpu_id in AFF0 */
>>      for ( i = 0 ; i < 32 ; i++ )
>> -        v->arch.vgic.private_irqs->v3.irouter[i] = affinity;
>> +        v->arch.vgic.private_irqs->v3.irouter[i] = v->vcpu_id & 
>> MPIDR_AFF0_MASK;
>
> In practice though it should be the same thing, right?
> I mean affinity == (v->vcpu_id & MPIDR_AFF0_MASK), right?

 Yes, affinity should hold vcpu number. Just to be inline
with what vgic irouter[] holds I changed it to v->vcpu_id & MPIDR_AFF0_MASK

Regards
Vijay

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