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Re: [Xen-devel] [PATCH v3 for-4.5 0/9] xen: arm: support for > 40-bit physical addressing

On Thu, Sep 18, 2014 at 5:39 AM, Ian Campbell <ian.campbell@xxxxxxxxxx> wrote:
> ARM64 systems can support up to 48-bits of physical address, but
> currently we configure both Stage-1 and Stage-2 for only 40-bits.
> However there are systems with peripherals mapped higher up, in order to
> support those we need to support 48-bits as output for stage-1 as well
> as input and output for stage-2. Stage-2 support is needed in order to
> map them 1:1 to dom0.
> Unfortunately as the last commit message explains in a bit more detail
> supporting larger input sizes on the p2m is a pain because it means we
> can no longer statically decide to use a 3-level p2m with 2 concatenated
> pages at the root and need to be able to support either that *or* a
> 4-level p2m with no root concatenation. There is simply no static choice
> which supports both 40- and 48-bits of IPA.
> So this series goes through the various functions which manipulate or
> walk page tables and makes them able to support a dynamic starting level
> and concatenation before switching arm64 to make the choice dependent on
> the h/w capabilities.
> This is somewhat loosely based on Vijay's original "Add 4-level page
> table for stage 2 translation" series but due to the need to switch to
> dynamic p2m levels not much of that remains.
> I haven't actually been able to track down a system with >42-bit PASize.
> Vijay, I'm hoping you can test this new version of the series on such a
> system/model (thanks for your feed back on the previous iteration).

Can you please share your code base for testing it?. I could not
find any branch here



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