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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v5 2/3] xen/arm: Add new driver for SCIF UART
Signed-off-by: Oleksandr Tyshchenko <oleksandr.tyshchenko@xxxxxxxxxxxxxxx>
Signed-off-by: Iurii Konovalenko <iurii.konovalenko@xxxxxxxxxxxxxxx>
Reviewed-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
config/arm32.mk | 1 +
xen/drivers/char/Makefile | 1 +
xen/drivers/char/scif-uart.c | 367 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 369 insertions(+)
create mode 100644 xen/drivers/char/scif-uart.c
diff --git a/config/arm32.mk b/config/arm32.mk
index 4f83a63..268ca9c 100644
--- a/config/arm32.mk
+++ b/config/arm32.mk
@@ -12,6 +12,7 @@ CFLAGS += -marm
HAS_PL011 := y
HAS_EXYNOS4210 := y
HAS_OMAP := y
+HAS_SCIF := y
HAS_NS16550 := y
# Use only if calling $(LD) directly.
diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile
index 911b788..9e94195 100644
--- a/xen/drivers/char/Makefile
+++ b/xen/drivers/char/Makefile
@@ -3,6 +3,7 @@ obj-$(HAS_NS16550) += ns16550.o
obj-$(HAS_PL011) += pl011.o
obj-$(HAS_EXYNOS4210) += exynos4210-uart.o
obj-$(HAS_OMAP) += omap-uart.o
+obj-$(HAS_SCIF) += scif-uart.o
obj-$(HAS_EHCI) += ehci-dbgp.o
obj-$(CONFIG_ARM) += dt-uart.o
obj-y += serial.o
diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c
new file mode 100644
index 0000000..1a1c496
--- /dev/null
+++ b/xen/drivers/char/scif-uart.c
@@ -0,0 +1,367 @@
+/*
+ * xen/drivers/char/scif-uart.c
+ *
+ * Driver for SCIF (Serial communication interface with FIFO)
+ * compatible UART.
+ *
+ * Oleksandr Tyshchenko <oleksandr.tyshchenko@xxxxxxxxxxxxxxx>
+ * Copyright (C) 2014, Globallogic.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <xen/console.h>
+#include <xen/errno.h>
+#include <xen/serial.h>
+#include <xen/init.h>
+#include <xen/irq.h>
+#include <xen/mm.h>
+#include <xen/delay.h>
+#include <asm/device.h>
+#include <asm/scif-uart.h>
+#include <asm/io.h>
+
+#define PARITY_NONE 0
+#define PARITY_EVEN 1
+#define PARITY_ODD 2
+
+#define scif_readb(uart, off) readb((uart)->regs + (off))
+#define scif_writeb(uart, off, val) writeb((val), (uart)->regs + (off))
+
+#define scif_readw(uart, off) readw((uart)->regs + (off))
+#define scif_writew(uart, off, val) writew((val), (uart)->regs + (off))
+
+static struct scif_uart {
+ unsigned int baud, clock_hz, data_bits, parity, stop_bits;
+ unsigned int irq;
+ char __iomem *regs;
+ struct irqaction irqaction;
+ struct vuart_info vuart;
+} scif_com = {0};
+
+static void scif_uart_interrupt(int irq, void *data, struct cpu_user_regs
*regs)
+{
+ struct serial_port *port = data;
+ struct scif_uart *uart = port->uart;
+ uint16_t status, ctrl;
+
+ ctrl = scif_readw(uart, SCIF_SCSCR);
+ status = scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND;
+ /* Ignore next flag if TX Interrupt is disabled */
+ if ( !(ctrl & SCSCR_TIE) )
+ status &= ~SCFSR_TDFE;
+
+ while ( status != 0 )
+ {
+ /* TX Interrupt */
+ if ( status & SCFSR_TDFE )
+ serial_tx_interrupt(port, regs);
+
+ /* RX Interrupt */
+ if ( status & (SCFSR_RDF | SCFSR_DR) )
+ serial_rx_interrupt(port, regs);
+
+ /* Error Interrupt */
+ if ( status & SCIF_ERRORS )
+ scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS);
+ if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER )
+ scif_writew(uart, SCIF_SCLSR, 0);
+
+ ctrl = scif_readw(uart, SCIF_SCSCR);
+ status = scif_readw(uart, SCIF_SCFSR) & ~SCFSR_TEND;
+ /* Ignore next flag if TX Interrupt is disabled */
+ if ( !(ctrl & SCSCR_TIE) )
+ status &= ~SCFSR_TDFE;
+ }
+}
+
+static void __init scif_uart_init_preirq(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+ unsigned int divisor;
+ uint16_t val;
+
+ /*
+ * Wait until last bit has been transmitted. This is needed for a smooth
+ * transition when we come from early printk
+ */
+ while ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TEND) );
+
+ /* Disable TX/RX parts and all interrupts */
+ scif_writew(uart, SCIF_SCSCR, 0);
+
+ /* Reset TX/RX FIFOs */
+ scif_writew(uart, SCIF_SCFCR, SCFCR_RFRST | SCFCR_TFRST);
+
+ /* Clear all errors and flags */
+ scif_readw(uart, SCIF_SCFSR);
+ scif_writew(uart, SCIF_SCFSR, 0);
+ scif_readw(uart, SCIF_SCLSR);
+ scif_writew(uart, SCIF_SCLSR, 0);
+
+ /* Select Baud rate generator output as a clock source */
+ scif_writew(uart, SCIF_SCSCR, SCSCR_CKE10);
+
+ /* Setup protocol format and Baud rate, select Asynchronous mode */
+ val = 0;
+ ASSERT( uart->data_bits >= 7 && uart->data_bits <= 8 );
+ if ( uart->data_bits == 7 )
+ val |= SCSMR_CHR;
+ else
+ val &= ~SCSMR_CHR;
+
+ ASSERT( uart->stop_bits >= 1 && uart->stop_bits <= 2 );
+ if ( uart->stop_bits == 2 )
+ val |= SCSMR_STOP;
+ else
+ val &= ~SCSMR_STOP;
+
+ ASSERT( uart->parity >= PARITY_NONE && uart->parity <= PARITY_ODD );
+ switch ( uart->parity )
+ {
+ case PARITY_NONE:
+ val &= ~SCSMR_PE;
+ break;
+
+ case PARITY_EVEN:
+ val |= SCSMR_PE;
+ break;
+
+ case PARITY_ODD:
+ val |= SCSMR_PE | SCSMR_ODD;
+ break;
+ }
+ scif_writew(uart, SCIF_SCSMR, val);
+
+ ASSERT( uart->clock_hz > 0 );
+ if ( uart->baud != BAUD_AUTO )
+ {
+ /* Setup desired Baud rate */
+ divisor = uart->clock_hz / (uart->baud << 4);
+ ASSERT( divisor >= 1 && divisor <= (uint16_t)UINT_MAX );
+ scif_writew(uart, SCIF_DL, (uint16_t)divisor);
+ /* Selects the frequency divided clock (SC_CLK external input) */
+ scif_writew(uart, SCIF_CKS, 0);
+ udelay(1000000 / uart->baud + 1);
+ }
+ else
+ {
+ /* Read current Baud rate */
+ divisor = scif_readw(uart, SCIF_DL);
+ ASSERT( divisor >= 1 && divisor <= (uint16_t)UINT_MAX );
+ uart->baud = uart->clock_hz / (divisor << 4);
+ }
+
+ /* Setup trigger level for TX/RX FIFOs */
+ scif_writew(uart, SCIF_SCFCR, SCFCR_RTRG11 | SCFCR_TTRG11);
+
+ /* Enable TX/RX parts */
+ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) |
+ SCSCR_TE | SCSCR_RE);
+}
+
+static void __init scif_uart_init_postirq(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+ int rc;
+
+ uart->irqaction.handler = scif_uart_interrupt;
+ uart->irqaction.name = "scif_uart";
+ uart->irqaction.dev_id = port;
+
+ if ( (rc = setup_irq(uart->irq, 0, &uart->irqaction)) != 0 )
+ dprintk(XENLOG_ERR, "Failed to allocated scif_uart IRQ %d\n",
+ uart->irq);
+
+ /* Clear all errors */
+ if ( scif_readw(uart, SCIF_SCFSR) & SCIF_ERRORS )
+ scif_writew(uart, SCIF_SCFSR, ~SCIF_ERRORS);
+ if ( scif_readw(uart, SCIF_SCLSR) & SCLSR_ORER )
+ scif_writew(uart, SCIF_SCLSR, 0);
+
+ /* Enable TX/RX and Error Interrupts */
+ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) |
+ SCSCR_TIE | SCSCR_RIE | SCSCR_REIE);
+}
+
+static void scif_uart_suspend(struct serial_port *port)
+{
+ BUG();
+}
+
+static void scif_uart_resume(struct serial_port *port)
+{
+ BUG();
+}
+
+static int scif_uart_tx_ready(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+ uint16_t cnt;
+
+ /* Check for empty space in TX FIFO */
+ if ( !(scif_readw(uart, SCIF_SCFSR) & SCFSR_TDFE) )
+ return 0;
+
+ /* Check number of data bytes stored in TX FIFO */
+ cnt = scif_readw(uart, SCIF_SCFDR) >> 8;
+ ASSERT( cnt >= 0 && cnt <= SCIF_FIFO_MAX_SIZE );
+
+ return (SCIF_FIFO_MAX_SIZE - cnt);
+}
+
+static void scif_uart_putc(struct serial_port *port, char c)
+{
+ struct scif_uart *uart = port->uart;
+
+ scif_writeb(uart, SCIF_SCFTDR, c);
+ /* Clear required TX flags */
+ scif_writew(uart, SCIF_SCFSR, scif_readw(uart, SCIF_SCFSR) &
+ ~(SCFSR_TEND | SCFSR_TDFE));
+}
+
+static int scif_uart_getc(struct serial_port *port, char *pc)
+{
+ struct scif_uart *uart = port->uart;
+
+ /* Check for available data bytes in RX FIFO */
+ if ( !(scif_readw(uart, SCIF_SCFSR) & (SCFSR_RDF | SCFSR_DR)) )
+ return 0;
+
+ *pc = scif_readb(uart, SCIF_SCFRDR);
+
+ /* dummy read */
+ scif_readw(uart, SCIF_SCFSR);
+ /* Clear required RX flags */
+ scif_writew(uart, SCIF_SCFSR, ~(SCFSR_RDF | SCFSR_DR));
+
+ return 1;
+}
+
+static int __init scif_uart_irq(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+
+ return ((uart->irq > 0) ? uart->irq : -1);
+}
+
+static const struct vuart_info *scif_vuart_info(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+
+ return &uart->vuart;
+}
+
+static void scif_uart_start_tx(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+
+ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) | SCSCR_TIE);
+}
+
+static void scif_uart_stop_tx(struct serial_port *port)
+{
+ struct scif_uart *uart = port->uart;
+
+ scif_writew(uart, SCIF_SCSCR, scif_readw(uart, SCIF_SCSCR) & ~SCSCR_TIE);
+}
+
+static struct uart_driver __read_mostly scif_uart_driver = {
+ .init_preirq = scif_uart_init_preirq,
+ .init_postirq = scif_uart_init_postirq,
+ .endboot = NULL,
+ .suspend = scif_uart_suspend,
+ .resume = scif_uart_resume,
+ .tx_ready = scif_uart_tx_ready,
+ .putc = scif_uart_putc,
+ .getc = scif_uart_getc,
+ .irq = scif_uart_irq,
+ .start_tx = scif_uart_start_tx,
+ .stop_tx = scif_uart_stop_tx,
+ .vuart_info = scif_vuart_info,
+};
+
+static int __init scif_uart_init(struct dt_device_node *dev,
+ const void *data)
+{
+ const char *config = data;
+ struct scif_uart *uart;
+ int res;
+ u64 addr, size;
+
+ if ( strcmp(config, "") )
+ printk("WARNING: UART configuration is not supported\n");
+
+ uart = &scif_com;
+
+ uart->clock_hz = SCIF_CLK_FREQ;
+ uart->baud = BAUD_AUTO;
+ uart->data_bits = 8;
+ uart->parity = PARITY_NONE;
+ uart->stop_bits = 1;
+
+ res = dt_device_get_address(dev, 0, &addr, &size);
+ if ( res )
+ {
+ printk("scif-uart: Unable to retrieve the base"
+ " address of the UART\n");
+ return res;
+ }
+
+ res = platform_get_irq(dev, 0);
+ if ( res < 0 )
+ {
+ printk("scif-uart: Unable to retrieve the IRQ\n");
+ return res;
+ }
+ uart->irq = res;
+
+ uart->regs = ioremap_nocache(addr, size);
+ if ( !uart->regs )
+ {
+ printk("scif-uart: Unable to map the UART memory\n");
+ return -ENOMEM;
+ }
+
+ uart->vuart.base_addr = addr;
+ uart->vuart.size = size;
+ uart->vuart.data_off = SCIF_SCFTDR;
+ uart->vuart.status_off = SCIF_SCFSR;
+ uart->vuart.status = SCFSR_TDFE;
+
+ /* Register with generic serial driver */
+ serial_register_uart(SERHND_DTUART, &scif_uart_driver, uart);
+
+ dt_device_set_used_by(dev, DOMID_XEN);
+
+ return 0;
+}
+
+static const char * const scif_uart_dt_compat[] __initconst =
+{
+ "renesas,scif",
+ NULL
+};
+
+DT_DEVICE_START(scif_uart, "SCIF UART", DEVICE_SERIAL)
+ .compatible = scif_uart_dt_compat,
+ .init = scif_uart_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.9.1
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