Re: [Xen-devel] RFC: [PATCH 1/3] Enhance platform support for PCI

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 12.03.15 at 11:33, <stefano.stabellini@xxxxxxxxxxxxx> wrote:
> On Thu, 12 Mar 2015, Jan Beulich wrote:
>> >>> On 11.03.15 at 19:26, <stefano.stabellini@xxxxxxxxxxxxx> wrote:
>> > On Mon, 23 Feb 2015, Jan Beulich wrote:
>> >> No - there can be multiple roots (i.e. host bridges) on a single
>> >> segment. Segments are - afaict - purely a scalability extension
>> >> allowing to overcome the 256 bus limit.
>> > 
>> > Actually this turns out to be wrong. On the PCI MCFG spec it is clearly
>> > stated:
>> > 
>> > "The MCFG table format allows for more than one memory mapped base
>> > address entry provided each entry (memory mapped configuration space
>> > base address allocation structure) corresponds to a unique PCI Segment
>> > Group consisting of 256 PCI buses. Multiple entries corresponding to a
>> > single PCI Segment Group is not allowed."
>> 
>> For one, what you quote is in no contradiction to what I said. All it
>> specifies is that there shouldn't be multiple MCFG table entries
>> specifying the same segment. Whether on any such segment there
>> is a single host bridge or multiple of them is of no interest here.
> 
> I thought that we had already established that one host bridge
> corresponds to one PCI config memory region, see the last sentence in
> http://marc.info/?l=xen-devel&m=142529695117142.  Did I misunderstand
> it?  If a host bridge has a 1:1 relationship with CFG space, then each
> MCFG entry would correspond to one host bridge and one segment.

No, that sentence doesn't imply what you appear to think. Within
the same segment (and, for ACPI's sake within the same MCFG
region) you could have multiple host bridges. And then what calls
itself a host bridge (via class code) may or may not be one - often
there are many devices calling themselves such even on a single
bus (and my prior sentence specifically means to exclude those).
And finally there are systems with their PCI roots expressed only
in ACPI, without any specific PCI device serving as the host bridge.
There it is most obvious that firmware assigns both segment and
bus numbers to its liking.

Jan


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