Re: [Xen-devel] [PATCH 07/12] xen: arm: Handle CP15 register traps from userspace

[Ian Campbell <ian.campbell@xxxxxxxxxx>]

On Wed, 2015-03-25 at 18:59 +0000, Julien Grall wrote:
> Hi Ian,
> 
> On 25/03/15 14:22, Ian Campbell wrote:
> > Previously userspace access to PM* would have been incorrectly (but
> > benignly) implemented as RAZ/WI when running on a 32-bit kernel and
> > would cause a hypervisor exception (host crash) when running a 64-bit
> > kernel (this was already solved via the fix to XSA-102).
> > 
> > CLIDR, CCSIDR, DCCISW, ACTLR, PMINTENSET, PMINTENCLR are EL1 only,
> > attempts to access from EL0 will trap to EL1 not to us, hence BUG_ON
> > is appropriate now.
> 
> For PMINTENSET and PMINTENCLR the spec (ARMv8 DDI0487A rev d) says:
> 
> "If MDCR_EL2.TPM==1, Non-secure accesses to this register will trap from
> EL1 and EL0 to EL2."

Yes, it appears you are right. It is rather strange that an EL1 register
should trap to EL2 when accessed from EL0, but it does indeed seem to
say that.

I suspect this is an errata in the spec, but I suppose we should take it
at its word.

> As we set to 1 MDCR_EL1.TPM, EL0 access will trap to Xen. So I think we
> should replace the BUG_ON to injected a exception.

Yes.

> Reading more the spec only ACTLR access from EL0 will trap to EL1. All
> access from EL0 to the others registers in the list above will trap to EL2.
> 
> Although, the ARMv7 spec seems to say to only valid access will be trapped.



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