Re: [Xen-devel] [PATCH V14 5/7] xen/arm: Instruction prefetch abort (X) mem_access event handling

[Julien Grall <julien.grall@xxxxxxxxxx>]

Hi Tamas,

On 26/03/2015 22:05, Tamas K Lengyel wrote:
> Add missing structure definition for iabt and update the trap handling
> mechanism to only inject the exception if the mem_access checker
> decides to do so.
>
> Signed-off-by: Tamas K Lengyel <tklengyel@xxxxxxxxxxxxx>
> Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
> Reviewed-by:  Julien Grall <julien.grall@xxxxxxxxxx>
IHMO, the Acked-by and Reviewed-by should not have been carried in this 
patch because of the change you made in v14 (mainly the TLB).
[..]

> +        /*
> +         * Flush the TLB to make sure the DTLB is clear before
> +         * doing GVA->IPA translation. If we got here because of
> +         * an entry only present in the ITLB, this translation may
> +         * still be inaccurate.
> +         */
> +        flush_tlb_domain(current->domain);
flush TLB domain is very expensive, it flushes TLBs on every CPU. While 
you may only need a flush on the current CPU.
Although, on ARMv8, there is no possibility to flush only DTLB or ITLB 
for aarch64. You have to do both at the same time. So the problem you 
are describing can't happen. After reading the ID_MMFR2_EL1, I 
understand that Unified TLB is strongly advice on ARMv8 so any DTLB/ITLB 
flush would flush the unified TLB for aarch32 guest.
This is different for ARMv7, it may be possible to have a split-TLB. The 
register ID_MMFR2 indicates if the platform implement unified TLB or 
harvard TLB. In the case of the former, any DTLB/ITLB flush will be 
perform on the unified TLB (see B4.2.2 in DDI406C.b).
So it would be possible to avoid the flush in most of the case.

Regards,

--
Julien Grall

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