Re: [Xen-devel] [PATCH v4 08/15] xen: arm: don't pretend to handle cache maintenance by set/way

[Julien Grall <julien.grall@xxxxxxxxxx>]

Hi Ian,

On 27/03/15 14:33, Ian Campbell wrote:
> We set HCR_EL2.TSW but only (sort of) handle 32-bit access to DCCISW
> but not the other two registers, nor any 64-bit access. Add handlers
> for all of these.

We don't set HCR_EL2.TSW so DCCISW is not trapped.

> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index c2dcb66..cf3d6cc 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -161,6 +161,11 @@
>   *
>   * - The device tree Xen compatible node is fully described under Linux
>   *   at Documentation/devicetree/bindings/arm/xen.txt.
> + *
> + * - Cache maintenaince operations by set/way ("dc isw|cisw|csw" and
> + *   the equivalent cp15 registers) are not available when running
> + *   under Xen and will result in an undefined instruction exception
> + *   delivered to the guest.
>   */

set/way operations is used by Linux ARM32 in order to flush all the
cache. Injecting an undefined instruction would make guest unusable.

Regards,

-- 
Julien Grall

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