From: Chen Baozi <baozich@xxxxxxxxx>
According to ARM CPUs bindings, the reg field should match the MPIDR's
affinity bits. We will use AFF0 and AFF1 when constructing the reg value
of the guest at the moment, for it is enough for the current max vcpu
number.
Signed-off-by: Chen Baozi <baozich@xxxxxxxxx>
---
tools/libxl/libxl_arm.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c
index c5088c4..8aa4815 100644
--- a/tools/libxl/libxl_arm.c
+++ b/tools/libxl/libxl_arm.c
@@ -272,6 +272,7 @@ static int make_cpus_node(libxl__gc *gc, void *fdt, int
nr_cpus,
const struct arch_info *ainfo)
{
int res, i;
+ uint64_t mpidr_aff;
res = fdt_begin_node(fdt, "cpus");
if (res) return res;
@@ -283,7 +284,16 @@ static int make_cpus_node(libxl__gc *gc, void *fdt, int
nr_cpus,
if (res) return res;
for (i = 0; i < nr_cpus; i++) {
- const char *name = GCSPRINTF("cpu@%d", i);
+ const char *name;
+
+ /*
+ * According to ARM CPUs bindings, the reg field should match
+ * the MPIDR's affinity bits. We will use AFF0 and AFF1 when
+ * constructing the reg value of the guest at the moment, for it
+ * is enough for the current max vcpu number.
+ */
+ mpidr_aff = (uint64_t)((i & 0x0f) | (((i >> 4) & 0xff) << 8));
