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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v2 12/15] xen/arm: gic: Store the necessary HW information per vGIC ...
... in order to decouple the vGIC driver from the GIC driver.
Each vGIC HW structure contains a boolean to indicate if the current GIC is
able to support this specific version of virtual GIC.
Helpers have been introduced in order to help the GIC to setup correctly
the vGIC. The GIC will have to call them to announce the support of this
specific version.
Also drop fields that become unecessary in each global state.
Signed-off-by: Julien Grall <julien.grall@xxxxxxxxxx>
---
Changes in v2:
- Patch added in replacement of "xen/arm: gic-v2: Move GICD,
GICC and GICV base address in gic_info ..." and "xen/arm:
gic-v3: Move Distributor and Re-Distributors info in gic_info
..."
---
xen/arch/arm/gic-hip04.c | 37 +++++++++++++--------------
xen/arch/arm/gic-v2.c | 37 +++++++++++++--------------
xen/arch/arm/gic-v3.c | 31 +++++++++++------------
xen/arch/arm/vgic-v2.c | 2 ++
xen/arch/arm/vgic-v3.c | 2 ++
xen/arch/arm/vgic.c | 16 ++++++++++++
xen/include/asm-arm/gic_v3_defs.h | 7 ++++++
xen/include/asm-arm/vgic.h | 53 +++++++++++++++++++++++++++++++++++++++
8 files changed, 130 insertions(+), 55 deletions(-)
diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
index 984726a..259c6d6 100644
--- a/xen/arch/arm/gic-hip04.c
+++ b/xen/arch/arm/gic-hip04.c
@@ -65,12 +65,9 @@
/* Global state */
static struct {
- paddr_t dbase; /* Address of distributor registers */
void __iomem * map_dbase; /* IO mapped Address of distributor registers */
- paddr_t cbase; /* Address of CPU interface registers */
void __iomem * map_cbase[2]; /* IO mapped Address of CPU interface
registers */
void __iomem * map_hbase; /* IO Address of virtual interface registers */
- paddr_t vbase; /* Address of virtual cpu interface registers */
spinlock_t lock;
} gicv2;
@@ -444,8 +441,8 @@ static int hip04gicv_setup(struct domain *d)
*/
if ( is_hardware_domain(d) )
{
- d->arch.vgic.dbase = gicv2.dbase;
- d->arch.vgic.cbase = gicv2.cbase;
+ d->arch.vgic.dbase = vgic_v2_hw.dbase;
+ d->arch.vgic.cbase = vgic_v2_hw.cbase;
}
else
{
@@ -461,16 +458,16 @@ static int hip04gicv_setup(struct domain *d)
* GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
*/
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase), 1,
- paddr_to_pfn(gicv2.vbase));
+ paddr_to_pfn(vgic_v2_hw.vbase));
if ( ret )
return ret;
if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- 2, paddr_to_pfn(gicv2.vbase + PAGE_SIZE));
+ 2, paddr_to_pfn(vgic_v2_hw.vbase + PAGE_SIZE));
else
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- 2, paddr_to_pfn(gicv2.vbase + SZ_64K));
+ 2, paddr_to_pfn(vgic_v2_hw.vbase + SZ_64K));
return ret;
}
@@ -676,14 +673,14 @@ static hw_irq_controller hip04gic_guest_irq_type = {
static int __init hip04gic_init(void)
{
int res;
- paddr_t hbase;
+ paddr_t hbase, dbase, cbase, vbase;
const struct dt_device_node *node = gicv2_info.node;
- res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
+ res = dt_device_get_address(node, 0, &dbase, NULL);
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the distributor");
- res = dt_device_get_address(node, 1, &gicv2.cbase, NULL);
+ res = dt_device_get_address(node, 1, &cbase, NULL);
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the CPU");
@@ -691,7 +688,7 @@ static int __init hip04gic_init(void)
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the hypervisor");
- res = dt_device_get_address(node, 3, &gicv2.vbase, NULL);
+ res = dt_device_get_address(node, 3, &vbase, NULL);
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the virtual CPU");
@@ -708,23 +705,23 @@ static int __init hip04gic_init(void)
" gic_hyp_addr=%"PRIpaddr"\n"
" gic_vcpu_addr=%"PRIpaddr"\n"
" gic_maintenance_irq=%u\n",
- gicv2.dbase, gicv2.cbase, hbase, gicv2.vbase,
+ dbase, cbase, hbase, vbase,
gicv2_info.maintenance_irq);
- if ( (gicv2.dbase & ~PAGE_MASK) || (gicv2.cbase & ~PAGE_MASK) ||
- (hbase & ~PAGE_MASK) || (gicv2.vbase & ~PAGE_MASK) )
+ if ( (dbase & ~PAGE_MASK) || (cbase & ~PAGE_MASK) ||
+ (hbase & ~PAGE_MASK) || (vbase & ~PAGE_MASK) )
panic("GIC-HIP04 interfaces not page aligned");
- gicv2.map_dbase = ioremap_nocache(gicv2.dbase, PAGE_SIZE);
+ gicv2.map_dbase = ioremap_nocache(dbase, PAGE_SIZE);
if ( !gicv2.map_dbase )
panic("GIC-HIP04: Failed to ioremap for GIC distributor\n");
- gicv2.map_cbase[0] = ioremap_nocache(gicv2.cbase, PAGE_SIZE);
+ gicv2.map_cbase[0] = ioremap_nocache(cbase, PAGE_SIZE);
if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gicv2.map_cbase[1] = ioremap_nocache(gicv2.cbase + SZ_64K, PAGE_SIZE);
+ gicv2.map_cbase[1] = ioremap_nocache(cbase + SZ_64K, PAGE_SIZE);
else
- gicv2.map_cbase[1] = ioremap_nocache(gicv2.cbase + PAGE_SIZE,
PAGE_SIZE);
+ gicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
if ( !gicv2.map_cbase[0] || !gicv2.map_cbase[1] )
panic("GIC-HIP04: Failed to ioremap for GIC CPU interface\n");
@@ -733,6 +730,8 @@ static int __init hip04gic_init(void)
if ( !gicv2.map_hbase )
panic("GIC-HIP04: Failed to ioremap for GIC Virtual interface\n");
+ vgic_v2_setup_hw(dbase, cbase, vbase);
+
/* Global settings: interrupt distributor */
spin_lock_init(&gicv2.lock);
spin_lock(&gicv2.lock);
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 6ec6602..4d94335 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -64,12 +64,9 @@
/* Global state */
static struct {
- paddr_t dbase; /* Address of distributor registers */
void __iomem * map_dbase; /* IO mapped Address of distributor registers */
- paddr_t cbase; /* Address of CPU interface registers */
void __iomem * map_cbase[2]; /* IO mapped Address of CPU interface
registers */
void __iomem * map_hbase; /* IO Address of virtual interface registers */
- paddr_t vbase; /* Address of virtual cpu interface registers */
spinlock_t lock;
} gicv2;
@@ -434,8 +431,8 @@ static int gicv2v_setup(struct domain *d)
*/
if ( is_hardware_domain(d) )
{
- d->arch.vgic.dbase = gicv2.dbase;
- d->arch.vgic.cbase = gicv2.cbase;
+ d->arch.vgic.dbase = vgic_v2_hw.dbase;
+ d->arch.vgic.cbase = vgic_v2_hw.cbase;
}
else
{
@@ -451,16 +448,16 @@ static int gicv2v_setup(struct domain *d)
* GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
*/
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase), 1,
- paddr_to_pfn(gicv2.vbase));
+ paddr_to_pfn(vgic_v2_hw.vbase));
if ( ret )
return ret;
if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- 2, paddr_to_pfn(gicv2.vbase + PAGE_SIZE));
+ 2, paddr_to_pfn(vgic_v2_hw.vbase + PAGE_SIZE));
else
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- 2, paddr_to_pfn(gicv2.vbase + SZ_64K));
+ 2, paddr_to_pfn(vgic_v2_hw.vbase + SZ_64K));
return ret;
}
@@ -662,14 +659,14 @@ static hw_irq_controller gicv2_guest_irq_type = {
static int __init gicv2_init(void)
{
int res;
- paddr_t hbase;
+ paddr_t hbase, dbase, cbase, vbase;
const struct dt_device_node *node = gicv2_info.node;
- res = dt_device_get_address(node, 0, &gicv2.dbase, NULL);
+ res = dt_device_get_address(node, 0, &dbase, NULL);
if ( res )
panic("GICv2: Cannot find a valid address for the distributor");
- res = dt_device_get_address(node, 1, &gicv2.cbase, NULL);
+ res = dt_device_get_address(node, 1, &cbase, NULL);
if ( res )
panic("GICv2: Cannot find a valid address for the CPU");
@@ -677,7 +674,7 @@ static int __init gicv2_init(void)
if ( res )
panic("GICv2: Cannot find a valid address for the hypervisor");
- res = dt_device_get_address(node, 3, &gicv2.vbase, NULL);
+ res = dt_device_get_address(node, 3, &vbase, NULL);
if ( res )
panic("GICv2: Cannot find a valid address for the virtual CPU");
@@ -694,23 +691,23 @@ static int __init gicv2_init(void)
" gic_hyp_addr=%"PRIpaddr"\n"
" gic_vcpu_addr=%"PRIpaddr"\n"
" gic_maintenance_irq=%u\n",
- gicv2.dbase, gicv2.cbase, hbase, gicv2.vbase,
+ dbase, cbase, hbase, vbase,
gicv2_info.maintenance_irq);
- if ( (gicv2.dbase & ~PAGE_MASK) || (gicv2.cbase & ~PAGE_MASK) ||
- (hbase & ~PAGE_MASK) || (gicv2.vbase & ~PAGE_MASK) )
+ if ( (dbase & ~PAGE_MASK) || (cbase & ~PAGE_MASK) ||
+ (hbase & ~PAGE_MASK) || (vbase & ~PAGE_MASK) )
panic("GICv2 interfaces not page aligned");
- gicv2.map_dbase = ioremap_nocache(gicv2.dbase, PAGE_SIZE);
+ gicv2.map_dbase = ioremap_nocache(dbase, PAGE_SIZE);
if ( !gicv2.map_dbase )
panic("GICv2: Failed to ioremap for GIC distributor\n");
- gicv2.map_cbase[0] = ioremap_nocache(gicv2.cbase, PAGE_SIZE);
+ gicv2.map_cbase[0] = ioremap_nocache(cbase, PAGE_SIZE);
if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gicv2.map_cbase[1] = ioremap_nocache(gicv2.cbase + SZ_64K, PAGE_SIZE);
+ gicv2.map_cbase[1] = ioremap_nocache(cbase + SZ_64K, PAGE_SIZE);
else
- gicv2.map_cbase[1] = ioremap_nocache(gicv2.cbase + PAGE_SIZE,
PAGE_SIZE);
+ gicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
if ( !gicv2.map_cbase[0] || !gicv2.map_cbase[1] )
panic("GICv2: Failed to ioremap for GIC CPU interface\n");
@@ -719,6 +716,8 @@ static int __init gicv2_init(void)
if ( !gicv2.map_hbase )
panic("GICv2: Failed to ioremap for GIC Virtual interface\n");
+ vgic_v2_setup_hw(dbase, cbase, vbase);
+
/* Global settings: interrupt distributor */
spin_lock_init(&gicv2.lock);
spin_lock(&gicv2.lock);
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index 1c38c02..73ea700 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -42,15 +42,8 @@
#include <asm/gic_v3_defs.h>
#include <asm/cpufeature.h>
-struct rdist_region {
- paddr_t base;
- paddr_t size;
- void __iomem *map_base;
-};
-
/* Global state */
static struct {
- paddr_t dbase; /* Address of distributor registers */
void __iomem *map_dbase; /* Mapped address of distributor registers */
struct rdist_region *rdist_regions;
uint32_t rdist_stride;
@@ -936,9 +929,9 @@ static int gicv_v3_init(struct domain *d)
{
unsigned int first_cpu = 0;
- d->arch.vgic.dbase = gicv3.dbase;
+ d->arch.vgic.dbase = vgic_v3_hw.dbase;
- d->arch.vgic.rdist_stride = gicv3.rdist_stride;
+ d->arch.vgic.rdist_stride = vgic_v3_hw.rdist_stride;
/*
* If the stride is not set, the default stride for GICv3 is 2 * 64K:
* - first 64k page for Control and Physical LPIs
@@ -949,9 +942,9 @@ static int gicv_v3_init(struct domain *d)
for ( i = 0; i < gicv3.rdist_count; i++ )
{
- paddr_t size = gicv3.rdist_regions[i].size;
+ paddr_t size = vgic_v3_hw.regions[i].size;
- d->arch.vgic.rdist_regions[i].base = gicv3.rdist_regions[i].base;
+ d->arch.vgic.rdist_regions[i].base = vgic_v3_hw.regions[i].base;
d->arch.vgic.rdist_regions[i].size = size;
/* Set the first CPU handled by this region */
@@ -959,7 +952,7 @@ static int gicv_v3_init(struct domain *d)
first_cpu += size / d->arch.vgic.rdist_stride;
}
- d->arch.vgic.nr_regions = gicv3.rdist_count;
+ d->arch.vgic.nr_regions = vgic_v3_hw.nr_rdist_regions;
}
else
{
@@ -1190,6 +1183,7 @@ static int __init gicv3_init(void)
int res, i;
uint32_t reg;
const struct dt_device_node *node = gicv3_info.node;
+ paddr_t dbase;
if ( !cpu_has_gicv3 )
{
@@ -1197,15 +1191,15 @@ static int __init gicv3_init(void)
return -ENODEV;
}
- res = dt_device_get_address(node, 0, &gicv3.dbase, NULL);
+ res = dt_device_get_address(node, 0, &dbase, NULL);
if ( res )
panic("GICv3: Cannot find a valid distributor address");
- if ( (gicv3.dbase & ~PAGE_MASK) )
+ if ( (dbase & ~PAGE_MASK) )
panic("GICv3: Found unaligned distributor address %"PRIpaddr"",
- gicv3.dbase);
+ dbase);
- gicv3.map_dbase = ioremap_nocache(gicv3.dbase, SZ_64K);
+ gicv3.map_dbase = ioremap_nocache(dbase, SZ_64K);
if ( !gicv3.map_dbase )
panic("GICv3: Failed to ioremap for GIC distributor\n");
@@ -1266,7 +1260,7 @@ static int __init gicv3_init(void)
" gic_maintenance_irq=%u\n"
" gic_rdist_stride=%#x\n"
" gic_rdist_regions=%d\n",
- gicv3.dbase, gicv3_info.maintenance_irq,
+ dbase, gicv3_info.maintenance_irq,
gicv3.rdist_stride, gicv3.rdist_count);
printk(" redistributor regions:\n");
for ( i = 0; i < gicv3.rdist_count; i++ )
@@ -1277,6 +1271,9 @@ static int __init gicv3_init(void)
i, r->base, r->base + r->size);
}
+ vgic_v3_setup_hw(dbase, gicv3.rdist_count, gicv3.rdist_regions,
+ gicv3.rdist_stride);
+
spin_lock_init(&gicv3.lock);
spin_lock(&gicv3.lock);
diff --git a/xen/arch/arm/vgic-v2.c b/xen/arch/arm/vgic-v2.c
index 9eecabc..029305a 100644
--- a/xen/arch/arm/vgic-v2.c
+++ b/xen/arch/arm/vgic-v2.c
@@ -31,6 +31,8 @@
#include <asm/gic.h>
#include <asm/vgic.h>
+struct vgic_v2_hw_config vgic_v2_hw;
+
static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info)
{
struct hsr_dabt dabt = info->dabt;
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index cfaedc1..5d295e4 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -50,6 +50,8 @@
*/
#define VGICD_CTLR_DEFAULT (GICD_CTLR_ARE_NS)
+struct vgic_v3_hw_config vgic_v3_hw;
+
static struct vcpu *vgic_v3_irouter_to_vcpu(struct domain *d, uint64_t irouter)
{
unsigned int vcpu_id;
diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index 23ea58d..08c5e45 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -85,13 +85,29 @@ int domain_vgic_init(struct domain *d, unsigned int nr_spis)
{
#ifdef HAS_GICV3
case GIC_V3:
+ if ( !vgic_v3_hw.enabled )
+ {
+ printk(XENLOG_G_ERR
+ "d%d: vGICv3 is not supported on this platform\n",
+ d->domain_id);
+ return -ENODEV;
+ }
d->arch.vgic.handler = &vgic_v3_ops;
break;
#endif
case GIC_V2:
+ if ( !vgic_v2_hw.enabled )
+ {
+ printk(XENLOG_G_ERR
+ "d%d: vGICv2 is not supported on this platform\n",
+ d->domain_id);
+ return -ENODEV;
+ }
d->arch.vgic.handler = &vgic_v2_ops;
break;
default:
+ printk(XENLOG_G_ERR "d%d: Unknown vGIC version %u\n",
+ d->domain_id, d->arch.vgic.version);
return -ENODEV;
}
diff --git a/xen/include/asm-arm/gic_v3_defs.h
b/xen/include/asm-arm/gic_v3_defs.h
index 556f114..42bdaa3 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -152,6 +152,13 @@
#define ICH_SGI_IRQ_SHIFT 24
#define ICH_SGI_IRQ_MASK 0xf
#define ICH_SGI_TARGETLIST_MASK 0xffff
+
+struct rdist_region {
+ paddr_t base;
+ paddr_t size;
+ void __iomem *map_base;
+};
+
#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
/*
diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h
index 4422a24..e107a42 100644
--- a/xen/include/asm-arm/vgic.h
+++ b/xen/include/asm-arm/vgic.h
@@ -20,6 +20,10 @@
#include <xen/bitops.h>
+#ifdef HAS_GICV3
+#include <asm/gic_v3_defs.h>
+#endif
+
struct pending_irq
{
/*
@@ -228,6 +232,55 @@ static inline int vgic_allocate_spi(struct domain *d)
extern void vgic_free_virq(struct domain *d, unsigned int virq);
+struct vgic_v2_hw_config
+{
+ bool_t enabled;
+ /* Distributor interface address */
+ paddr_t dbase;
+ /* CPU interface address */
+ paddr_t cbase;
+ /* Virtual CPU interface address */
+ paddr_t vbase;
+};
+
+extern struct vgic_v2_hw_config vgic_v2_hw;
+
+static inline void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase,
+ paddr_t vbase)
+{
+ vgic_v2_hw.enabled = 1;
+ vgic_v2_hw.dbase = dbase;
+ vgic_v2_hw.cbase = cbase;
+ vgic_v2_hw.vbase = vbase;
+}
+
+#ifdef HAS_GICV3
+struct vgic_v3_hw_config
+{
+ bool_t enabled;
+ /* Distributor interface address */
+ paddr_t dbase;
+ /* Re-distributor regions */
+ unsigned int nr_rdist_regions;
+ const struct rdist_region *regions;
+ uint32_t rdist_stride; /* Re-distributor stride */
+};
+
+extern struct vgic_v3_hw_config vgic_v3_hw;
+
+static inline void vgic_v3_setup_hw(paddr_t dbase,
+ unsigned int nr_rdist_regions,
+ const struct rdist_region *regions,
+ uint32_t rdist_stride)
+{
+ vgic_v3_hw.enabled = 1;
+ vgic_v3_hw.dbase = dbase;
+ vgic_v3_hw.nr_rdist_regions = nr_rdist_regions;
+ vgic_v3_hw.regions = regions;
+ vgic_v3_hw.rdist_stride = rdist_stride;
+}
+#endif
+
#endif /* __ASM_ARM_VGIC_H__ */
/*
--
2.4.3
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