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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH v6 13/31] xen/arm: ITS: implement hw_irq_controller for LPIs
From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
Implements hw_irq_controller api's required
to handle LPI's.
Changed callbacks gic_host_irq_type and gic_guest_irq_type
to gic_get_host_irq_type and gic_get_guest_irq_type
in gic_hw_operations, which returns
hw_irq_controller based on irq type (SPI or LPI).
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
CC: Zoltan Kiss <zoltan.kiss@xxxxxxxxxx>
---
v6: - Moved this patch #15 in v5 to patch #9
- Introduce inv command
- Moved msi_desc helper functions to separate
"xen/arm: ITS: Introduce msi_desc for LPIs"
- Exported LPI hw_irq_controller structure and removed
helper function to access.
v5: - Fixed review comments
- Exposed gicv3_[host|guest]_irq_end and hook to its
v4: - Implement separate hw_irq_controller for LPIs
- Drop setting LPI affinity
- virq and vid are moved under union
- Introduced inv command handling
- its_device is stored in irq_desc
---
xen/arch/arm/gic-hip04.c | 14 +++-
xen/arch/arm/gic-v2.c | 14 +++-
xen/arch/arm/gic-v3-its.c | 133 +++++++++++++++++++++++++++++++++++++
xen/arch/arm/gic-v3.c | 25 ++++++-
xen/arch/arm/gic.c | 14 +++-
xen/include/asm-arm/gic-its.h | 1 +
xen/include/asm-arm/gic.h | 4 +-
xen/include/asm-arm/gic_v3_defs.h | 2 +
8 files changed, 196 insertions(+), 11 deletions(-)
diff --git a/xen/arch/arm/gic-hip04.c b/xen/arch/arm/gic-hip04.c
index b5811e6..98fdeee 100644
--- a/xen/arch/arm/gic-hip04.c
+++ b/xen/arch/arm/gic-hip04.c
@@ -630,6 +630,16 @@ static hw_irq_controller hip04gic_guest_irq_type = {
.set_affinity = hip04gic_irq_set_affinity,
};
+static hw_irq_controller *hip04gic_get_host_irq_type(unsigned int irq)
+{
+ return &hip04gic_host_irq_type;
+}
+
+static hw_irq_controller *hip04gic_get_guest_irq_type(unsigned int irq)
+{
+ return &hip04gic_guest_irq_type;
+}
+
static int __init hip04gic_init(void)
{
int res;
@@ -712,8 +722,8 @@ const static struct gic_hw_operations hip04gic_ops = {
.save_state = hip04gic_save_state,
.restore_state = hip04gic_restore_state,
.dump_state = hip04gic_dump_state,
- .gic_host_irq_type = &hip04gic_host_irq_type,
- .gic_guest_irq_type = &hip04gic_guest_irq_type,
+ .gic_get_host_irq_type = hip04gic_get_host_irq_type,
+ .gic_get_guest_irq_type = hip04gic_get_guest_irq_type,
.eoi_irq = hip04gic_eoi_irq,
.deactivate_irq = hip04gic_dir_irq,
.read_irq = hip04gic_read_irq,
diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c
index 364343d..fe02334 100644
--- a/xen/arch/arm/gic-v2.c
+++ b/xen/arch/arm/gic-v2.c
@@ -616,6 +616,16 @@ static hw_irq_controller gicv2_guest_irq_type = {
.set_affinity = gicv2_irq_set_affinity,
};
+static hw_irq_controller *gicv2_get_host_irq_type(unsigned int irq)
+{
+ return &gicv2_host_irq_type;
+}
+
+static hw_irq_controller *gicv2_get_guest_irq_type(unsigned int irq)
+{
+ return &gicv2_guest_irq_type;
+}
+
static int __init gicv2_init(void)
{
int res;
@@ -698,8 +708,8 @@ const static struct gic_hw_operations gicv2_ops = {
.save_state = gicv2_save_state,
.restore_state = gicv2_restore_state,
.dump_state = gicv2_dump_state,
- .gic_host_irq_type = &gicv2_host_irq_type,
- .gic_guest_irq_type = &gicv2_guest_irq_type,
+ .gic_get_host_irq_type = gicv2_get_host_irq_type,
+ .gic_get_guest_irq_type = gicv2_get_guest_irq_type,
.eoi_irq = gicv2_eoi_irq,
.deactivate_irq = gicv2_dir_irq,
.read_irq = gicv2_read_irq,
diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
index f14c0f4..0865a93 100644
--- a/xen/arch/arm/gic-v3-its.c
+++ b/xen/arch/arm/gic-v3-its.c
@@ -349,6 +349,19 @@ post:
its_wait_for_range_completion(its, cmd, next_cmd);
}
+static void its_send_inv(struct its_device *dev, u32 event)
+{
+ its_cmd_block cmd;
+ struct its_collection *col = dev_event_to_col(dev, event);
+
+ memset(&cmd, 0x0, sizeof(its_cmd_block));
+ cmd.inv.cmd = GITS_CMD_INV;
+ cmd.inv.devid = dev->device_id;
+ cmd.inv.event = event;
+
+ its_send_single_command(dev->its, &cmd, col);
+}
+
static void its_send_mapd(struct its_device *dev, int valid)
{
its_cmd_block cmd;
@@ -425,6 +438,126 @@ static void its_send_discard(struct its_device *dev, u32
event)
its_send_single_command(dev->its, &cmd, col);
}
+static void its_flush_and_invalidate_prop(struct irq_desc *desc, u8 *cfg)
+{
+ struct its_device *its_dev = irqdesc_get_its_device(desc);
+ u32 vid = irqdesc_get_lpi_event(desc);
+
+ ASSERT(vid < its_dev->event_map.nr_lpis);
+
+ /*
+ * Make the above write visible to the redistributors.
+ * And yes, we're flushing exactly: One. Single. Byte.
+ * Humpf...
+ */
+ if ( gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING )
+ clean_and_invalidate_dcache_va_range(cfg, sizeof(*cfg));
+ else
+ dsb(ishst);
+
+ its_send_inv(its_dev, vid);
+}
+
+static void its_set_lpi_state(struct irq_desc *desc, int enable)
+{
+ u8 *cfg;
+
+ ASSERT(spin_is_locked(&its_lock));
+
+ cfg = gic_rdists->prop_page + desc->irq - FIRST_GIC_LPI;
+ if ( enable )
+ *cfg |= LPI_PROP_ENABLED;
+ else
+ *cfg &= ~LPI_PROP_ENABLED;
+
+ its_flush_and_invalidate_prop(desc, cfg);
+}
+
+static void its_irq_enable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&its_lock, flags);
+ clear_bit(_IRQ_DISABLED, &desc->status);
+ dsb(sy);
+ its_set_lpi_state(desc, 1);
+ spin_unlock_irqrestore(&its_lock, flags);
+}
+
+static void its_irq_disable(struct irq_desc *desc)
+{
+ unsigned long flags;
+
+ ASSERT(spin_is_locked(&desc->lock));
+
+ spin_lock_irqsave(&its_lock, flags);
+ its_set_lpi_state(desc, 0);
+ set_bit(_IRQ_DISABLED, &desc->status);
+ spin_unlock_irqrestore(&its_lock, flags);
+}
+
+static unsigned int its_irq_startup(struct irq_desc *desc)
+{
+ its_irq_enable(desc);
+
+ return 0;
+}
+
+static void its_irq_shutdown(struct irq_desc *desc)
+{
+ its_irq_disable(desc);
+}
+
+static void its_irq_ack(struct irq_desc *desc)
+{
+ /* No ACK -- reading IAR has done this for us */
+}
+
+static void its_host_irq_end(struct irq_desc *desc)
+{
+ /* Lower the priority */
+ gicv3_eoi_irq(desc);
+ /* LPIs does not have active state. Do not deactivate */
+}
+
+static void its_guest_irq_end(struct irq_desc *desc)
+{
+ gicv3_eoi_irq(desc);
+}
+
+static void its_irq_set_affinity(struct irq_desc *desc, const cpumask_t *mask)
+{
+ /*TODO: Yet to support */
+ printk(XENLOG_G_WARNING
+ "%pv: ITS: Setting Affinity of LPI is not supported\n", current);
+
+ return;
+}
+
+const hw_irq_controller its_host_lpi_type = {
+ .typename = "gic-its",
+ .startup = its_irq_startup,
+ .shutdown = its_irq_shutdown,
+ .enable = its_irq_enable,
+ .disable = its_irq_disable,
+ .ack = its_irq_ack,
+ .end = its_host_irq_end,
+ .set_affinity = its_irq_set_affinity,
+};
+
+const hw_irq_controller its_guest_lpi_type = {
+ .typename = "gic-its",
+ .startup = its_irq_startup,
+ .shutdown = its_irq_shutdown,
+ .enable = its_irq_enable,
+ .disable = its_irq_disable,
+ .ack = its_irq_ack,
+ .end = its_guest_irq_end,
+ .set_affinity = its_irq_set_affinity,
+};
+
/*
* How we allocate LPIs:
*
diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
index e90e0cc..c3b1a7c 100644
--- a/xen/arch/arm/gic-v3.c
+++ b/xen/arch/arm/gic-v3.c
@@ -40,6 +40,7 @@
#include <asm/device.h>
#include <asm/gic.h>
#include <asm/gic_v3_defs.h>
+#include <asm/gic-its.h>
#include <asm/cpufeature.h>
/* Global state */
@@ -54,6 +55,8 @@ static struct {
} gicv3;
static struct gic_info gicv3_info;
+extern const hw_irq_controller its_host_lpi_type;
+extern const hw_irq_controller its_guest_lpi_type;
/* per-cpu re-distributor base */
DEFINE_PER_CPU(struct rdist, rdist);
@@ -440,7 +443,7 @@ static void gicv3_mask_irq(struct irq_desc *irqd)
gicv3_poke_irq(irqd, GICD_ICENABLER);
}
-static void gicv3_eoi_irq(struct irq_desc *irqd)
+void gicv3_eoi_irq(struct irq_desc *irqd)
{
/* Lower the priority */
WRITE_SYSREG32(irqd->irq, ICC_EOIR1_EL1);
@@ -1136,6 +1139,22 @@ static const hw_irq_controller gicv3_guest_irq_type = {
.set_affinity = gicv3_irq_set_affinity,
};
+static hw_irq_controller *gicv3_get_host_irq_type(unsigned int irq)
+{
+ if ( gic_is_lpi(irq) )
+ return &its_host_lpi_type;
+
+ return &gicv3_host_irq_type;
+}
+
+static hw_irq_controller *gicv3_get_guest_irq_type(unsigned int irq)
+{
+ if ( gic_is_lpi(irq) )
+ return &its_guest_lpi_type;
+
+ return &gicv3_guest_irq_type;
+}
+
static int __init cmp_rdist(const void *a, const void *b)
{
const struct rdist_region *l = a, *r = a;
@@ -1295,8 +1314,8 @@ static const struct gic_hw_operations gicv3_ops = {
.save_state = gicv3_save_state,
.restore_state = gicv3_restore_state,
.dump_state = gicv3_dump_state,
- .gic_host_irq_type = &gicv3_host_irq_type,
- .gic_guest_irq_type = &gicv3_guest_irq_type,
+ .gic_get_host_irq_type = gicv3_get_host_irq_type,
+ .gic_get_guest_irq_type = gicv3_get_guest_irq_type,
.eoi_irq = gicv3_eoi_irq,
.deactivate_irq = gicv3_dir_irq,
.read_irq = gicv3_read_irq,
diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c
index 2199963..16d43ec 100644
--- a/xen/arch/arm/gic.c
+++ b/xen/arch/arm/gic.c
@@ -103,6 +103,16 @@ void gic_restore_state(struct vcpu *v)
gic_restore_pending_irqs(v);
}
+static inline hw_irq_controller *get_host_hw_irq_controller(unsigned int irq)
+{
+ return gic_hw_ops->gic_get_host_irq_type(irq);
+}
+
+static inline hw_irq_controller *get_guest_hw_irq_controller(unsigned int irq)
+{
+ return gic_hw_ops->gic_get_guest_irq_type(irq);
+}
+
/*
* needs to be called with a valid cpu_mask, ie each cpu in the mask has
* already called gic_cpu_init
@@ -127,7 +137,7 @@ void gic_route_irq_to_xen(struct irq_desc *desc, const
cpumask_t *cpu_mask,
ASSERT(test_bit(_IRQ_DISABLED, &desc->status));
ASSERT(spin_is_locked(&desc->lock));
- desc->handler = gic_hw_ops->gic_host_irq_type;
+ desc->handler = get_host_hw_irq_controller(desc->irq);
gic_set_irq_properties(desc, cpu_mask, priority);
}
@@ -158,7 +168,7 @@ int gic_route_irq_to_guest(struct domain *d, unsigned int
virq,
test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) )
goto out;
- desc->handler = gic_hw_ops->gic_guest_irq_type;
+ desc->handler = get_guest_hw_irq_controller(desc->irq);
set_bit(_IRQ_GUEST, &desc->status);
gic_set_irq_properties(desc, cpumask_of(v_target->processor), priority);
diff --git a/xen/include/asm-arm/gic-its.h b/xen/include/asm-arm/gic-its.h
index 3599c76..7a46e21 100644
--- a/xen/include/asm-arm/gic-its.h
+++ b/xen/include/asm-arm/gic-its.h
@@ -279,6 +279,7 @@ void irqdesc_set_lpi_event(struct irq_desc *desc, unsigned
id);
unsigned int irqdesc_get_lpi_event(struct irq_desc *desc);
struct its_device *irqdesc_get_its_device(struct irq_desc *desc);
void irqdesc_set_its_device(struct irq_desc *desc, struct its_device *dev);
+bool_t is_valid_collection(struct domain *d, uint32_t col);
int its_init(struct rdist_prop *rdists);
int its_cpu_init(void);
int its_add_device(u32 devid, u32 nr_ites, struct dt_device_node *dt_its);
diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h
index d39e1b3..6ece7cc 100644
--- a/xen/include/asm-arm/gic.h
+++ b/xen/include/asm-arm/gic.h
@@ -317,10 +317,10 @@ struct gic_hw_operations {
void (*dump_state)(const struct vcpu *);
/* hw_irq_controller to enable/disable/eoi host irq */
- hw_irq_controller *gic_host_irq_type;
+ const hw_irq_controller *(*gic_get_host_irq_type)(unsigned int irq);
/* hw_irq_controller to enable/disable/eoi guest irq */
- hw_irq_controller *gic_guest_irq_type;
+ const hw_irq_controller *(*gic_get_guest_irq_type)(unsigned int irq);
/* End of Interrupt */
void (*eoi_irq)(struct irq_desc *irqd);
diff --git a/xen/include/asm-arm/gic_v3_defs.h
b/xen/include/asm-arm/gic_v3_defs.h
index 1153509..d950a1f 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -200,6 +200,8 @@ struct rdist_prop {
DECLARE_PER_CPU(struct rdist, rdist);
+void gicv3_eoi_irq(struct irq_desc *irqd);
+
#endif /* __ASM_ARM_GIC_V3_DEFS_H__ */
/*
--
1.7.9.5
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