[Xen-devel] [PATCH v7 26/28] xen/arm: ITS: Map ITS translation space

[vijay.kilari@xxxxxxxxx]

From: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>

ITS translation space contains GITS_TRANSLATER register
which is written by device to raise LPI. This space needs
to mapped to every domain address space for all physical
ITS available,so that device can access GITS_TRANSLATER
register using SMMU.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@xxxxxxxxxxxxxxxxxx>
Acked-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
---
v7: - Added comment on allowing CPU to access GITS_TRANSLATER
v6: - corrected typo in commit message
    - Removed check for dom0
---
 xen/arch/arm/vgic-v3-its.c |   49 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 4f907d2..042592f 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++ b/xen/arch/arm/vgic-v3-its.c
@@ -828,6 +828,53 @@ static const struct mmio_handler_ops 
vgic_gits_mmio_handler = {
     .write_handler = vgic_v3_gits_mmio_write,
 };
 
+/*
+ * Map the 64K ITS translation space in guest.
+ * This is required purely for device smmu writes.
+*/
+
+static int vits_map_translation_space(struct domain *d)
+{
+    uint64_t addr, size;
+    int ret;
+
+    ASSERT(is_domain_direct_mapped(d));
+
+    addr = d->arch.vgic.vits->gits_base + SZ_64K;
+    size = SZ_64K;
+
+    /* For DomU translation space is mapped 1:1.
+     *
+     * As per spec IHI0069A, 8.1.3 there is undefined behavior when CPU
+     * writes to this register with wrong access size.
+     * Currently the page table are shared between the processor and the SMMU,
+     * So that means that a domain will be able to deadlock the processor
+     * and therefore the whole platform.
+     *
+     * TODO: A CPU should *never* be able to write to the GITS_TRANSLATER
+     * register. We have to make sure a guest cannot directly write to the HW.
+     * So we should never expose GITS_TRANSLATER into the processor page table.
+     * Which means we should not share page tables between the processor
+     * and the SMMU
+     *
+     * TODO: Also Handle DomU mapping
+     */
+    ret = map_mmio_regions(d,
+                           paddr_to_pfn(addr & PAGE_MASK),
+                           DIV_ROUND_UP(size, PAGE_SIZE),
+                           paddr_to_pfn(addr & PAGE_MASK));
+
+    if ( ret )
+    {
+         dprintk(XENLOG_G_ERR, "vITS: Unable to map to"
+                 " 0x%"PRIx64" - 0x%"PRIx64" to dom%d\n",
+                 addr & PAGE_MASK, PAGE_ALIGN(addr + size) - 1,
+                 d->domain_id);
+    }
+
+    return ret;
+}
+
 int vits_domain_init(struct domain *d)
 {
     struct vgic_its *vits;
@@ -882,7 +929,7 @@ int vits_domain_init(struct domain *d)
 
     register_mmio_handler(d, &vgic_gits_mmio_handler, vits->gits_base, SZ_64K);
 
-    return 0;
+    return vits_map_translation_space(d);
 }
 
 void vits_domain_free(struct domain *d)
-- 
1.7.9.5


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