Re: [Xen-devel] [PATCH for-4.6] p2m/ept: Set the A bit only if PML is enabled

[Tim Deegan <tim@xxxxxxx>]

At 20:47 +0100 on 16 Sep (1442436442), Andrew Cooper wrote:
> On 16/09/2015 09:47, Ross Lagerwall wrote:
> > Since commit 191b3f3344ee ("p2m/ept: enable PML in p2m-ept for
> > log-dirty"), the A and D bits of EPT paging entries are set
> > unconditionally, regardless of whether PML is enabled or not. This
> > causes a regression in Xen 4.6 on some processors due to Intel Errata
> > AVR41 -- HVM guests get severe memory corruption when the A bit is
> > set. The errata affects the Atom C2000 family (Avaton).
> 
> ^ Due to incorrect TLB flushing on mov to cr3.
> 
> >
> > Instead, only set the bits if PML is enabled.
> 
> (You have missed a SoB)
> 
> While this certainly does fix the issue, I am not certain if it is the
> correct fix; It relies on no affected systems actually supporting PML.
> 
> The root issue is that ept a/d bits may not be used, even just as
> software-defined bits on these systems, and calling this out should be
> as specific quirk against Avoton systems, rather than being related to PML.

Rather than making thinsg slower for everyone, perhaps we could just
work around this one broken chip?  E.g. by intercepting CR3 writes and
explicitly flushing the TLB?

Cheers,

Tim.

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