[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH resend] vt-d: Fix IM bit mask and unmask of Fault Event Control Register.
Bit 0:29 in Fault Event Control Register are 'Reserved and Preserved', software cannot write 0 to it unconditionally. Software must preserve the value read for writes. Signed-off-by: Quan Xu <quan.xu@xxxxxxxxx> Acked-by: Yang Zhang <yang.z.zhang@xxxxxxxxx> --- xen/drivers/passthrough/vtd/iommu.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/xen/drivers/passthrough/vtd/iommu.c b/xen/drivers/passthrough/vtd/iommu.c index 3d98fea..f31d41b 100644 --- a/xen/drivers/passthrough/vtd/iommu.c +++ b/xen/drivers/passthrough/vtd/iommu.c @@ -992,10 +992,13 @@ static void dma_msi_unmask(struct irq_desc *desc) { struct iommu *iommu = desc->action->dev_id; unsigned long flags; + u32 sts; /* unmask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, 0); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts &= ~DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 0; } @@ -1004,10 +1007,13 @@ static void dma_msi_mask(struct irq_desc *desc) { unsigned long flags; struct iommu *iommu = desc->action->dev_id; + u32 sts; /* mask it */ spin_lock_irqsave(&iommu->register_lock, flags); - dmar_writel(iommu->reg, DMAR_FECTL_REG, DMA_FECTL_IM); + sts = dmar_readl(iommu->reg, DMAR_FECTL_REG); + sts |= DMA_FECTL_IM; + dmar_writel(iommu->reg, DMAR_FECTL_REG, sts); spin_unlock_irqrestore(&iommu->register_lock, flags); iommu->msi.msi_attrib.host_masked = 1; } -- 1.8.3.2 _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx http://lists.xen.org/xen-devel
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