Re: [Xen-devel] [PATCH] x86/ept: defer enabling of EPT A/D bit until PML get enabled.

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 16.10.15 at 11:17, <kai.huang@xxxxxxxxxxxxxxx> wrote:
> On 10/16/2015 04:17 PM, Jan Beulich wrote:
>>>>> On 16.10.15 at 04:21, <kai.huang@xxxxxxxxxxxxxxx> wrote:
>>> +void vmx_domain_update_eptp(struct domain *d)
>>> +{
>>> +    struct p2m_domain *p2m = p2m_get_hostp2m(d);
>>> +    struct vcpu *v;
>>> +
>>> +    ASSERT(atomic_read(&d->pause_count));
>> This should imo check controller_pause_count.
> This function is called between domain_pause and domain_unpause, and 
> domain_pause increases d->pause_count, not d->controller_pause_count, so 
> we should check d->pause_count, right?

Ah, okay - I thought the pause was tool stack initiated.

>>>   static void ept_flush_pml_buffers(struct p2m_domain *p2m)
>>>   {
>>> +    /* Domain must have been paused */
>>> +    ASSERT(atomic_read(&p2m->domain->pause_count));
>> This seems unrelated - did you really mean it to go into this patch?
> This function is also supposed to be called when domain is paused, so 
> making it consistent with ept_enable{disable}_pml, I also added the 
> ASSERT here. Is this reasonable?

Then you need to explicitly mention that in the commit message.

Jan


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