[Xen-devel] [PATCH v2 00/11] xen/arm: Bunch of fixes for the vGIC emulation

[Julien Grall <julien.grall@xxxxxxxxxx>]

Hi all,

The main purpose of this patch series is to fix the access to any register when
the user doesn't write at the base offset of the registers.

At the same time, I took the opportunity to re-arrange the emulation and
dropping any registers which don't exist or not required by the spec.

This series is based on "xen/arm: Support 32-bit access for 64-bit registers"
[1]. I've provided a branch with the 2 series applied:

git://xenbits.xen.org/people/julieng/xen-unstable.git branch gic-emulation-v2

Note that the 2 first patch what meant to be present in the previous version
but I messed up my git format-patch.

For all the changes see in each patch.

Sincerely yours,

[1] http://lists.xen.org/archives/html/xen-devel/2015-11/msg02188.html

Julien Grall (11):
  xen/arm: vgic-v2: Implement correctly ICFGR{0,1} read-only
  xen/arm: vgic-v3: Don't try to emulate IROUTER which doesn't exist in
    the spec
  xen/arm: vgic-v3: Use the correct offset GICR_IGRPMODR0
  xen/arm: vgic-v3: Only emulate identification registers required by
    the spec
  xen/arm: vgic: Properly emulate the full register
  xen/arm: vgic-v3: Remove GICR_MOVALLR and GICR_MOVLPIR
  xen/arm: vgic: Re-order the register emulations to match the memory
    map
  xen/arm: vgic-v3: Emulate read to GICD_ICACTIVER<n>
  xen/arm: vgic-v3: Remove spurious return in GICR_INVALLR
  xen/arm: vgic-v3: Don't implement write-only register read as zero
  xen/arm: vgic-v3: Make clear that GICD_*SPI_* registers are reserved

 xen/arch/arm/vgic-v2.c            | 254 +++++++------
 xen/arch/arm/vgic-v3.c            | 733 +++++++++++++++++++++++++-------------
 xen/include/asm-arm/gic.h         |   2 +
 xen/include/asm-arm/gic_v3_defs.h |  19 +-
 xen/include/asm-arm/vgic-emul.h   |  24 ++
 5 files changed, 658 insertions(+), 374 deletions(-)
 create mode 100644 xen/include/asm-arm/vgic-emul.h

-- 
2.1.4


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