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Re: [Xen-devel] [PATCH] iommu/quirk: disable shared EPT for Sandybridge and earlier processors.

On 26/11/15 10:39, Jan Beulich wrote:
>>>> On 26.11.15 at 11:27, <andrew.cooper3@xxxxxxxxxx> wrote:
>> On 26/11/15 08:45, Jan Beulich wrote:
>>>>>> On 25.11.15 at 16:58, <malcolm.crossley@xxxxxxxxxx> wrote:
>>>> On 25/11/15 15:38, Jan Beulich wrote:
>>>>>>>> On 25.11.15 at 16:13, <andrew.cooper3@xxxxxxxxxx> wrote:
>>>>>> On 25/11/15 10:49, Jan Beulich wrote:
>>>>>>> And finally I'm not fully convinced using CPU model info to deduce
>>>>>>> chipset behavior is entirely correct (albeit perhaps in practice it'll
>>>>>>> be fine except maybe when running Xen itself virtualized).
>>>>>> What else would you suggest? I can't think of any better identifying
>>>>>> information.
>>>>> Chipset IDs / revisions?
>>>> In this case the IOMMU is integrated into the Sandybridge-EP processor 
>>>> itself.
>>> Which doesn't preclude it to be identified via PCI device ID - after all
>>> there are dozens of processor integrated PCI devices. Looking at
>>> one of my systems,
>>> 00:05.0 System peripheral [0880]: Intel Corporation Sandy Bridge Address 
>> Map, VTd_Misc, System Management [8086:3c28] (rev 07)
>>> 80:05.0 System peripheral [0880]: Intel Corporation Sandy Bridge Address 
>> Map, VTd_Misc, System Management [8086:3c28] (rev 07)
>>> could be a candidate (we already key a quirk on this device in
>>> pci_vtd_quirk()).
>> These are fine for server variants, but not for desktop variants, both
>> of which we have seen in use.
> And I gave them only as an example that keying off of PCI IDs
> would be possible. A complete list would of course need to be
> compiled (but I think we could simply derive it from the list of IDs
> we already deal with in quirks.c).

That is not my point.  The Desktop variants do not expose their
internals as PCI devices.

Keying on the host bridge might be an option.

Also, on further consideration, the better fix (however we identify the
affected systems) would be to quirk the IOMMUs themselves into not
claiming 2M/1G superpage support.

Otherwise, when we do eventually get superpage IOMMU mapping support in
the API, the performance regression will creep back in.


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