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Re: [Xen-devel] Crash in set_cpu_sibling_map() booting Xen 4.6.0 on Fusion



I tested on VMware Fusion with 3, 4 and 8 CPUs, and it works in all cases.

(XEN) Xen version 4.6.1-pre ( 4.6.1~pre-1skyport1)
(eswierk@xxxxxxxxxxxxxxxxxx) (gcc (Debian 5.2.1-19.1skyport1) 5.2.1
20150930) debug=n Wed Dec  2 07:22:20 PST 2015
(XEN) Bootloader: SYSLINUX 4.05 20140113
(XEN) Command line: xen console=com1,vga com1=115200 no-bootscrub
dom0_mem=2048M,max:2048M loglvl=all cpuinfo=1
(XEN) Video information:
(XEN)  VGA is text mode 80x25, font 8x16
(XEN) Disc information:
(XEN)  Found 1 MBR signatures
(XEN)  Found 1 EDD information structures
(XEN) Xen-e820 RAM map:
(XEN)  0000000000000000 - 000000000009f800 (usable)
(XEN)  000000000009f800 - 00000000000a0000 (reserved)
(XEN)  00000000000dc000 - 0000000000100000 (reserved)
(XEN)  0000000000100000 - 00000000bfef0000 (usable)
(XEN)  00000000bfef0000 - 00000000bfeff000 (ACPI data)
(XEN)  00000000bfeff000 - 00000000bff00000 (ACPI NVS)
(XEN)  00000000bff00000 - 00000000c0000000 (usable)
(XEN)  00000000f0000000 - 00000000f8000000 (reserved)
(XEN)  00000000fec00000 - 00000000fec10000 (reserved)
(XEN)  00000000fee00000 - 00000000fee01000 (reserved)
(XEN)  00000000fffe0000 - 0000000100000000 (reserved)
(XEN)  0000000100000000 - 00000001c0000000 (usable)
(XEN) ACPI: RSDP 000F6A10, 0024 (r2 PTLTD )
(XEN) ACPI: XSDT BFEF030B, 0054 (r1 INTEL  440BX     6040000 VMW   1324272)
(XEN) ACPI: FACP BFEFEE73, 00F4 (r4 INTEL  440BX     6040000 PTL     F4240)
(XEN) ACPI: DSDT BFEF05B1, E8C2 (r1 PTLTD  Custom    6040000 MSFT  3000001)
(XEN) ACPI: FACS BFEFFFC0, 0040
(XEN) ACPI: BOOT BFEF0589, 0028 (r1 PTLTD  $SBFTBL$  6040000  LTP        1)
(XEN) ACPI: APIC BFEF050F, 007A (r1 PTLTD   APIC    6040000  LTP        0)
(XEN) ACPI: MCFG BFEF04D3, 003C (r1 PTLTD  $PCITBL$  6040000  LTP        1)
(XEN) ACPI: SRAT BFEF03C3, 0110 (r2 VMWARE MEMPLUG   6040000 VMW         1)
(XEN) ACPI: WAET BFEF039B, 0028 (r1 VMWARE VMW WAET  6040000 VMW         1)
(XEN) System RAM: 6143MB (6291004kB)
(XEN) SRAT: PXM 0 -> APIC 00 -> Node 0
(XEN) SRAT: PXM 0 -> APIC 02 -> Node 0
(XEN) SRAT: PXM 0 -> APIC 04 -> Node 0
(XEN) SRAT: PXM 0 -> APIC 06 -> Node 0
(XEN) SRAT: Node 0 PXM 0 0-a0000
(XEN) SRAT: Node 0 PXM 0 100000-10000000
(XEN) SRAT: Node 0 PXM 0 10000000-c0000000
(XEN) SRAT: Node 0 PXM 0 100000000-1c0000000
(XEN) NUMA: Allocated memnodemap from 1bdc50000 - 1bdc52000
(XEN) NUMA: Using 8 for the hash shift.
(XEN) Domain heap initialised
(XEN) found SMP MP-table at 000f6a80
(XEN) DMI present.
(XEN) Using APIC driver default
(XEN) ACPI: PM-Timer IO Port: 0x1008
(XEN) ACPI: SLEEP INFO: pm1x_cnt[1:1004,1:0], pm1x_evt[1:1000,1:0]
(XEN) ACPI:             wakeup_vec[bfefffcc], vec_size[20]
(XEN) ACPI: Local APIC address 0xfee00000
(XEN) ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
(XEN) Processor #0 6:6 APIC version 21
(XEN) ACPI: LAPIC (acpi_id[0x01] lapic_id[0x02] enabled)
(XEN) Processor #2 6:6 APIC version 21
(XEN) ACPI: LAPIC (acpi_id[0x02] lapic_id[0x04] enabled)
(XEN) Processor #4 6:6 APIC version 21
(XEN) ACPI: LAPIC (acpi_id[0x03] lapic_id[0x06] enabled)
(XEN) Processor #6 6:6 APIC version 21
(XEN) ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1])
(XEN) ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
(XEN) ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
(XEN) ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
(XEN) ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
(XEN) IOAPIC[0]: apic_id 1, version 17, address 0xfec00000, GSI 0-23
(XEN) ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge)
(XEN) ACPI: IRQ0 used by override.
(XEN) ACPI: IRQ2 used by override.
(XEN) Enabling APIC mode:  Flat.  Using 1 I/O APICs
(XEN) ERST table was not found
(XEN) Using ACPI (MADT) for SMP configuration information
(XEN) SMP: Allowing 4 CPUs (0 hotplug CPUs)
(XEN) IRQ limits: 24 GSI, 760 MSI/MSI-X
(XEN) Not enabling x2APIC: depends on iommu_supports_eim.
(XEN) CPU: Physical Processor ID: 0
(XEN) CPU: L1 I cache: 32K, L1 D cache: 32K
(XEN) CPU: L2 cache: 256K
(XEN) CPU: L3 cache: 6144K
(XEN) xstate_init: using cntxt_size: 0x340 and states: 0x7
(XEN) CPU0: No MCE banks present. Machine check support disabled
(XEN) Using scheduler: SMP Credit Scheduler (credit)
(XEN) Initializing CPU#0
(XEN) Detected 2592.669 MHz processor.
(XEN) Initing memory sharing.
(XEN) alt table ffff82d0802bd090 -> ffff82d0802be2c0
(XEN) PCI: MCFG configuration 0: base f0000000 segment 0000 buses 00 - 7f
(XEN) PCI: MCFG area at f0000000 reserved in E820
(XEN) PCI: Using MCFG for segment 0000 bus 00-7f
(XEN) I/O virtualisation disabled
(XEN) CPU0: Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz stepping 01
(XEN) nr_sockets: 7
(XEN) ENABLING IO-APIC IRQs
(XEN)  -> Using new ACK method
(XEN) ..TIMER: vector=0xF0 apic1=0 pin1=2 apic2=-1 pin2=-1
(XEN) Platform timer is 3.579MHz ACPI PM Timer
(XEN) Allocated console ring of 32 KiB.
(XEN) mwait-idle: MWAIT substates: 0x10
(XEN) mwait-idle: v0.4 model 0x46
(XEN) mwait-idle: lapic_timer_reliable_states 0xffffffff
(XEN) VMX: Supported advanced features:
(XEN)  - APIC TPR shadow
(XEN)  - Extended Page Tables (EPT)
(XEN)  - Virtual-Processor Identifiers (VPID)
(XEN)  - Virtual NMI
(XEN)  - MSR direct-access bitmap
(XEN)  - Unrestricted Guest
(XEN) HVM: ASIDs enabled.
(XEN) HVM: VMX enabled
(XEN) HVM: Hardware Assisted Paging (HAP) not detected
(XEN) HVM: PVH mode not supported on this platform
(XEN) CPU 0 APIC 0 -> Node 0
(XEN) CPU 1 APIC 2 -> Node 0
(XEN) Booting processor 1/2 eip 8f000
(XEN) Initializing CPU#1
(XEN) CPU: Physical Processor ID: 2
(XEN) CPU: L1 I cache: 32K, L1 D cache: 32K
(XEN) CPU: L2 cache: 256K
(XEN) CPU: L3 cache: 6144K
(XEN) CPU1: No MCE banks present. Machine check support disabled
(XEN) CPU1: Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz stepping 01
(XEN) CPU 2 APIC 4 -> Node 0
(XEN) Booting processor 2/4 eip 8f000
(XEN) Initializing CPU#2
(XEN) CPU: Physical Processor ID: 4
(XEN) CPU: L1 I cache: 32K, L1 D cache: 32K
(XEN) CPU: L2 cache: 256K
(XEN) CPU: L3 cache: 6144K
(XEN) CPU2: No MCE banks present. Machine check support disabled
(XEN) CPU2: Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz stepping 01
(XEN) CPU 3 APIC 6 -> Node 0
(XEN) Booting processor 3/6 eip 8f000
(XEN) Initializing CPU#3
(XEN) CPU: Physical Processor ID: 6
(XEN) CPU: L1 I cache: 32K, L1 D cache: 32K
(XEN) CPU: L2 cache: 256K
(XEN) CPU: L3 cache: 6144K
(XEN) CPU3: No MCE banks present. Machine check support disabled
(XEN) CPU3: Intel(R) Core(TM) i7-4960HQ CPU @ 2.60GHz stepping 01
(XEN) Brought up 4 CPUs
(XEN) ACPI sleep modes: S3
(XEN) VPMU: disabled
(XEN) Dom0 has maximum 600 PIRQs
(XEN) NX (Execute Disable) protection active
(XEN) *** LOADING DOMAIN 0 ***
(XEN)  Xen  kernel: 64-bit, lsb, compat32
(XEN)  Dom0 kernel: 64-bit, PAE, lsb, paddr 0x1000000 -> 0x2e00000
(XEN) PHYSICAL MEMORY ARRANGEMENT:
(XEN)  Dom0 alloc.:   00000001b4000000->00000001b8000000 (504788 pages
to be allocated)
(XEN)  Init. ramdisk: 00000001bf3d4000->00000001bffffc00
(XEN) VIRTUAL MEMORY ARRANGEMENT:
(XEN)  Loaded kernel: ffffffff81000000->ffffffff82e00000
(XEN)  Init. ramdisk: ffffffff82e00000->ffffffff83a2bc00
(XEN)  Phys-Mach map: ffffffff83a2c000->ffffffff83e2c000
(XEN)  Start info:    ffffffff83e2c000->ffffffff83e2c4b4
(XEN)  Page tables:   ffffffff83e2d000->ffffffff83e50000
(XEN)  Boot stack:    ffffffff83e50000->ffffffff83e51000
(XEN)  TOTAL:         ffffffff80000000->ffffffff84000000
(XEN)  ENTRY ADDRESS: ffffffff81e1e1f0
(XEN) Dom0 has maximum 4 VCPUs
(XEN) Std. Loglevel: All
(XEN) Guest Loglevel: Nothing (Rate-limited: Errors and warnings)
(XEN) Xen is relinquishing VGA console.
(XEN) *** Serial input -> DOM0 (type 'CTRL-a' three times to switch
input to Xen)
(XEN) Freed 288kB init memory.
mapping kernel into physical memory
about to get started...

--Ed



On Wed, Dec 2, 2015 at 5:48 AM, Jan Beulich <JBeulich@xxxxxxxx> wrote:
>>>> On 24.11.15 at 21:28, <eswierk@xxxxxxxxxxxxxxxxxx> wrote:
>> RFC. Boot tested on VMware Fusion, and on a 2-socket Xeon server.
>
> Mind trying this one instead?
>
> Jan
>
> --- unstable.orig/xen/arch/x86/mpparse.c
> +++ unstable/xen/arch/x86/mpparse.c
> @@ -89,19 +89,14 @@ void __init set_nr_cpu_ids(unsigned int
>
>  void __init set_nr_sockets(void)
>  {
> -    /*
> -     * Count the actual cpus in the socket 0 and use it to calculate 
> nr_sockets
> -     * so that the latter will be always >= the actual socket number in the
> -     * system even when APIC IDs from MP table are too sparse.
> -     */
> -    unsigned int cpus = bitmap_weight(phys_cpu_present_map.mask,
> -                                      boot_cpu_data.x86_max_cores *
> -                                      boot_cpu_data.x86_num_siblings);
> -
> -    if ( cpus == 0 )
> -        cpus = 1;
> -
> -    nr_sockets = DIV_ROUND_UP(num_processors + disabled_cpus, cpus);
> +       nr_sockets = last_physid(phys_cpu_present_map)
> +                    / boot_cpu_data.x86_max_cores
> +                    / boot_cpu_data.x86_num_siblings + 1;
> +       if (disabled_cpus)
> +               nr_sockets += (disabled_cpus - 1)
> +                             / boot_cpu_data.x86_max_cores
> +                             / boot_cpu_data.x86_num_siblings + 1;
> +       printk(XENLOG_DEBUG "nr_sockets: %u\n", nr_sockets);
>  }
>
>  /*
> --- unstable.orig/xen/include/asm-x86/mpspec.h
> +++ unstable/xen/include/asm-x86/mpspec.h
> @@ -43,6 +43,19 @@ typedef struct physid_mask physid_mask_t
>  #define physid_isset(physid, map)              test_bit(physid, (map).mask)
>  #define physid_test_and_set(physid, map)       test_and_set_bit(physid, 
> (map).mask)
>
> +#define first_physid(map)                      find_first_bit((map).mask, \
> +                                                              MAX_APICS)
> +#define next_physid(id, map)                   find_next_bit((map).mask, \
> +                                                             MAX_APICS, (id) 
> + 1)
> +#define last_physid(map) ({ \
> +       const unsigned long *mask = (map).mask; \
> +       unsigned int id, last = MAX_APICS; \
> +       for (id = find_first_bit(mask, MAX_APICS); id < MAX_APICS; \
> +            id = find_next_bit(mask, MAX_APICS, (id) + 1)) \
> +               last = id; \
> +       last; \
> +})
> +
>  #define physids_and(dst, src1, src2)           bitmap_and((dst).mask, 
> (src1).mask, (src2).mask, MAX_APICS)
>  #define physids_or(dst, src1, src2)            bitmap_or((dst).mask, 
> (src1).mask, (src2).mask, MAX_APICS)
>  #define physids_clear(map)                     bitmap_zero((map).mask, 
> MAX_APICS)
>
>

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