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Re: [Xen-devel] [PATCH v2 0/3] VPMU fixes

On 12/07/2015 04:24 PM, Kleen, Andi wrote:
I'm not aware of that specific quirk on Nehalem. Standard perf has a workaround 
for the errata below, but it sounds different from what you have.

But if it's a NHM/WSM problem your model numbers are certainly not enough.

That's exactly the problem that we are having --- we don't know who exactly is affected, including whether it's limited to Nehalem.

You always need some kind of limiter for the PMI because it is possible to 
program the PMU that PMIs/NMIs appear back-to-back and lock up the system. But 
just programming them to 1 is not enough in this case, really have to be 
limited (perf both accounts and limits the frequency in time and the total CPU 
consumption of the PMI).

Are you referring to 14c63f17b1 / update_perf_cpu_limits()?

I think if you have such a generic limiter it would likely be able to handle 
this issue too.

In theory I think we shouldn't need to do this since when guest's VCPU is descheduled its PMU registers are no longer loaded into HW. So if the guest is programming PMU in such a way that it can no longer do any useful work --- well, that's the guest's problem.

The quirk that we have in Xen is apparently trying to prevent system lock-up.

I should also note that this only observed in HVM (i.e. with VMX) so perhaps this is something specific to virtualization. E.g. getting a PMI while executing a VMRUN or something...

Comments of the Nehalem workaround in the main perf code:

* Workaround for:
  *   Intel Errata AAK100 (model 26)
  *   Intel Errata AAP53  (model 30)
  *   Intel Errata BD53   (model 44)
  * The official story:
  *   These chips need to be 'reset' when adding counters by programming the
  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
  *   in sequence on the same PMC or on different PMCs.

These look like errata for *incorrect* counting and so it's up to guests to work around these (which the guests do, provided they have intel_pmu_nhm_workaround(), or an equivalent in another OS).


  * In practise it appears some of these events do in fact count, and
  * we need to programm all 4 events.

          * The Errata requires below steps:
          * 2) Configure 4 PERFEVTSELx with the magic events and clear
          *    the corresponding PMCx;
          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;


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