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Re: [Xen-devel] [PATCH v2] xen/arm64: Fix incorrect memory region size in TCR_EL2

Hi Shanker,

On 14/03/16 16:10, Shanker Donthineni wrote:
The maximum and minimum values for TxSZ depend on level of
translation as per AArch64 Virtual Memory System Architecture.
According to ARM specification DDI0487A_h (sec D4.2.2, page 1752),
the minimum TxSZ value is 16. If TxSZ is programmed to a value
smaller than 16 then it is IMPLEMENTATION DEFINED.

This patch sets T0SZ to (64-48)bits since XEN uses all 4 levels
to cover 48bit (256TB) virtual address instead of value zero.

Signed-off-by: Shanker Donthineni <shankerd@xxxxxxxxxxxxxx>

Acked-by: Julien Grall <julien.grall@xxxxxxx>


Changed since v1:
     Edit commit descriprtion.

  xen/arch/arm/arm64/head.S | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 19fa2bb..946e2c9 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -342,8 +342,8 @@ skip_bss:
           * Top byte is used
           * PT walks use Inner-Shareable accesses,
           * PT walks are write-back, write-allocate in both cache levels,
-         * Full 64-bit address space goes through this table. */
-        ldr   x0, 
+         * 48-bit virtual address space goes through this table. */
+        ldr   x0, 
          /* ID_AA64MMFR0_EL1[3:0] (PARange) corresponds to TCR_EL2[18:16] (PS) 
          mrs   x1, ID_AA64MMFR0_EL1
          bfi   x0, x1, #16, #3

Julien Grall

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