Re: [Xen-devel] [PATCH v4 08/26] xen/x86: Generate deep dependencies of features

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 23.03.16 at 17:36, <andrew.cooper3@xxxxxxxxxx> wrote:
> +        # SSE2 was also re-specified as core for 64bit.  The AESNI and SHA
> +        # instruction groups are documented to require checking for SSE2
> +        # support as a prerequisite.
> +        SSE2: [SSE3, LM, AESNI, SHA],

No idea why I didn't notice this in v3 already: Are you referring to
"The SHA extensions require only XMM state support on operating
systems, similar to SSE2 instructions"? I don't think this can be read
to mean that SSE2 is a prereq. Instead to me this means that there
are no requirements to the OS beyond supporting SSE register
state and exception handling.

Similarly for AESNI it refers to "Checking for SSE/SSE2 Support",
which in turn says "Check that the processor supports the SSE
and/or SSE2 extensions" - note the "and/or" there and again in the
following referral to the actual CPUID bits.

Similarly SSE3 then only depends on SSE, ...

> +        # AMD K10 processors has SSE3 and SSE4A.  Bobcat/Barcelona processors
> +        # subsequently included SSSE3, and Bulldozer subsequently included
> +        # SSE4_1.  Intel have never shipped SSE4A.
> +        SSE3: [SSSE3, SSE4_1, SSE4_2, SSE4A],

... as does SSSE3 (despite its name).

SSE4.1 is different indeed: They require us to check SSE3 and SSSE3
along with SSE4.1.

SSE4.2 is even more complicated due to the CRC32 and POPCNT
special cases (which also implies that the latter two may need to
become dependents of SSE4.2).

Jan


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