Re: [Xen-devel] [for-4.7] xen/arm: Force broadcast of TLB and instruction cache maintenance instructions

[Julien Grall <julien.grall@xxxxxxx>]

Hi Konrad,

On 25/04/2016 19:22, Konrad Rzeszutek Wilk wrote:
> On Mon, Apr 18, 2016 at 10:29:51AM +0100, Julien Grall wrote:
> > UP guest usually uses TLB instruction to flush only on the local CPU. The
> > TLB flush won't be broadcasted across all the CPUs within the same
> > innershareable domain.
> >
> > When the vCPU is migrated between different CPUs, it may be rescheduled
> > to a previous CPU where the TLB has not been flushed. The TLB may
> > contain stale entries which will result to translate incorrectly a VA to
> > IPA or even cause TLB conflicts.
> >
> > To avoid a such situation, always set HCR_EL2.FB which will force the
> > broadcast of TLB and instruction cache maintenance instructions.
> > Cheers,
> >
> > Signed-off-by: Julien Grall <julien.grall@xxxxxxx>

> I presume this needs an Release-Ack ?
That's right. I would also like to have an acked-by/reviewed-by from 
Stefano as he was concerned about the performance impact of this patch.
Cheers,

--
Julien Grall

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