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Re: [Xen-devel] [RFC 13/16] xen/arm: arm64: Add Cortex-A53 cache errata workaround

Hello Stefano,

On 21/05/16 15:40, Stefano Stabellini wrote:
On Thu, 5 May 2016, Julien Grall wrote:
+       bool "Cortex-A53: 819472: Store exclusive instructions might cause data 
+       default y
+       depends on ARM_64
+       help
+         This option adds an alternative code sequence to work around ARM
+         erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
+         present when it is connected to a coherent interconnect.
+         If the processor is executing a load and store exclusive sequence at
+         the same time as a processor in another cluster is executing a cache
+         maintenance operation to the same address, then this erratum might
+         cause data corruption.
+         The workaround promotes data cache clean instructions to
+         data cache clean-and-invalidate.
+         Please note that this does not necessarily enable the workaround,
+         as it depends on the alternative framework, which will only patch
+         the kernel if an affected CPU is detected.
+         If unsure, say Y.

I am not sure whether we want to go into this level of configuration.
You have already introduced ALTERNATIVE, so somebody which might not
want any workarounds can disable them all. Otherwise do you have use
cases for allowing people to only enable some and not all?

Alternative is not selectable by the user.

If you are a distro you need to enable them all. If you are in the
embedded space and you are working with one specific SoC, you can
manually disable any workarounds you don't want.

The main purpose of KConfig is to be able to disable manually certain options without hacking the code.

I also find the Kconfig very helpful for describing each erratum and the impact to hypervisor.


Julien Grall

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