Re: [Xen-devel] [PATCH v2 12/15] xen/arm: arm64: Add Cortex-A53 cache errata workaround

[Julien Grall <julien.grall@xxxxxxx>]

Hello,

Please configure your e-mail client to quote properly.

On 24/05/2016 03:46, Chenxiao Zhao wrote:
> On Mon, May 23, 2016 at 7:22 AM Julien Grall <julien.grall@xxxxxxx
> <mailto:julien.grall@xxxxxxx>> wrote:
>      /*
>     +<<<<<<< HEAD
>     +=======
>     + * icache_line_size - get the minimum I-cache line size from the
>     CTR register.
>     + */
>     +       .macro  icache_line_size, reg, tmp
>     +       mrs     \tmp, ctr_el0                   // read CTR
>     +       and     \tmp, \tmp, #0xf                // cache line size
>     encoding
>     +       mov     \reg, #4                        // bytes per word
>     +       lsl     \reg, \reg, \tmp                // actual cache line
>     size
>     +       .endm
>     +
>     +/*
>     + *     flush_icache_range(start,end)
>     + *
>     + *     Ensure that the I and D caches are coherent within specified
>     region.
>     + *     This is typically used when code has been written to a
>     memory region,
>     + *     and will be executed.
>     + *
>     + *     - start   - virtual start address of region
>     + *     - end     - virtual end address of region
>     + */
>     +ENTRY(flush_icache_range)
>     +       dcache_line_size x2, x3
>     +       sub     x3, x2, #1
>     +       bic     x4, x0, x3
>     +1:
>     +alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE
>     +       dc      cvau, x4
>     +alternative_else
>     +       dc      civac, x4
>     +alternative_endif
>     +       add     x4, x4, x2
>     +       cmp     x4, x1
>     +       b.lo    1b
>     +       dsb     ish
>     +
>     +       icache_line_size x2, x3
>     +       sub     x3, x2, #1
>     +       bic     x4, x0, x3
>     +1:
>     +       ic      ivau, x4                // invalidate I line PoU
>     +       add     x4, x4, x2
>     +       cmp     x4, x1
>     +       b.lo    1b
>     +       dsb     ish
>     +       isb
>     +       mov     x0, #0
>     +       ret
>     +ENDPROC(flush_icache_range)
>     +
>     +/*
>     +>>>>>>> 3b39ae7... xen/arm: arm64: Add Cortex-A53 cache errata
>
>     workaround
> This patch has a conflict, only can patched manually.
Whilst this patch contain a conflict because I have not rebased 
correctly, it applies without any issue and compile on ARM64.
This is because >>>> are part of the comments. I will sent a new version 
of this patch.
Regards,

--
Julien Grall

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