Re: [Xen-devel] [PATCH v4 3/4] xen:arm: arm64: Add correct MPIDR_HWID_MASK value for ARM64

[Julien Grall <julien.grall@xxxxxxx>]

Hi Wei,

On 31/05/16 03:54, Wei Chen wrote:
> Currently, MPIDR_HWID_MASK is using the bit definition of AArch32
> MPIDR register. But from D7.2.67 of ARM ARM (DDI 0487A.i) we can see
> there are 4 levels of affinity on AArch64 whilst AArch32 has only 3.
> So, this value is not correct when Xen is running on AArch64.
>
> Now, we use the value 0xff00ffffff for this macro on AArch64. But
> neither of this value and its bitwise invert value can be used in mov
> instruction with the encoding of {imm16:shift} or {imms:immr}. So we
> have to use ldr to load the bitwise invert value to register.
>
> The details of mov immediate encoding are listed in C4.2.5 of ARM ARM
> (DDI 0487A.i).
>
> Signed-off-by: Wei Chen <Wei.Chen@xxxxxxxxxx>
Reviewed-by: Julien Grall <julien.grall@xxxxxxx>

Regards,

> ---
> v3-->v4:
> 1. Update version number.
>
> v2-->v3:
> 1. Add version information of mentioned ARM ARM.
>
> v1-->v2: Address Julien's comments
> 1. Fix typos in commit messages.
> 2. Explain valid MPIDR_HWID_MASK value in AArch64.
> 3. Simply explain mov immediate encoding.
> ---
>   xen/arch/arm/arm64/head.S       | 2 +-
>   xen/include/asm-arm/processor.h | 4 ++++
>   2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index d5831f2..3090beb 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -270,7 +270,7 @@ common_start:
>           tbz   x0, _MPIDR_SMP, 1f     /* Multiprocessor extension not 
> supported? */
>           tbnz  x0, _MPIDR_UP, 1f      /* Uniprocessor system? */
>
> -        mov   x13, #(~MPIDR_HWID_MASK)
> +        ldr   x13, =(~MPIDR_HWID_MASK)
>           bic   x24, x0, x13           /* Mask out flags to get CPU ID */
>   1:
>
> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
> index b4cce7e..284ad6a 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -18,7 +18,11 @@
>   #define MPIDR_SMP           (_AC(1,U) << _MPIDR_SMP)
>   #define MPIDR_AFF0_SHIFT    (0)
>   #define MPIDR_AFF0_MASK     (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
> +#ifdef CONFIG_ARM_64
> +#define MPIDR_HWID_MASK     _AC(0xff00ffffff,UL)
> +#else
>   #define MPIDR_HWID_MASK     _AC(0xffffff,U)
> +#endif
>   #define MPIDR_INVALID       (~MPIDR_HWID_MASK)
>   #define MPIDR_LEVEL_BITS    (8)
--
Julien Grall

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