Re: [Xen-devel] [PATCH V7 2/3] drivers/pl011: Use combination of UARTRIS and UARTMSC instead of UARTMIS

[Julien Grall <julien.grall@xxxxxxx>]

Hi Shanker,

On 07/06/2016 20:04, Shanker Donthineni wrote:
> The Masked interrupt status register (UARTMIS) is not described in ARM
> SBSA 2.x document. Anding of two registers UARTMSC and UARTRIS values
> gives the same information as register UARTMIS.
>
> UARTRIS, UARTMSC and UARTMIS definitions are found in PrimeCell UART
> PL011 (Revision: r1p4).
>  - 3.3.10 Interrupt mask set/clear register, UARTIMSC
>  - 3.3.11 Raw interrupt status register, UARTRIS
>  - 3.3.12 Masked interrupt status register, UARTMIS
>
> This change is necessary for driver to be SBSA compliant v2.x without
> affecting the current driver functionality.
>
> Signed-off-by: Shanker Donthineni <shankerd@xxxxxxxxxxxxxx>
> ---
> Changes since v1:
>  Added a new function to return an interrupt status.
>
>  xen/drivers/char/pl011.c | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
> index 6a3c21b..86fc463 100644
> --- a/xen/drivers/char/pl011.c
> +++ b/xen/drivers/char/pl011.c
> @@ -50,14 +50,21 @@ static struct pl011 {
>  #define PARITY_MARK  (PEN|SPS)
>  #define PARITY_SPACE (PEN|EPS|SPS)
>
> +/* To compatible with SBSA v2.x document, all accesses should be 32-bit */
This comment does not belong to this patch but the next one (#3).

Regards,

--
Julien Grall

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