Re: [Xen-devel] [PATCH] x86/cpuid: AVX-512 Feature Detection

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 29/06/16 11:03, Jan Beulich wrote:
>>>> On 29.06.16 at 11:50, <andrew.cooper3@xxxxxxxxxx> wrote:
>> On 29/06/16 03:20, Luwei Kang wrote:
>>> --- a/xen/tools/gen-cpuid.py
>>> +++ b/xen/tools/gen-cpuid.py
>>> @@ -235,6 +235,10 @@ def crunch_numbers(state):
>>>          # subsequent instruction groups may only be VEX encoded.
>>>          AVX: [FMA, FMA4, F16C, AVX2, XOP],
>>>  
>>> +        # AVX-512 is an extention of AVX2 and it depends on AVX2 available.
>>> +        AVX2: [AVX512F, AVX512DQ, AVX512IFMA, AVX512PF, AVX512ER, AVX512CD,
>>> +                AVX512BW, AVX512VL, AVX512VBMI],
>> I think this needs adjusting.  AVX512F is the base feature and
>> indication of extra xstate, while all other AVX512 features (e.g.
>> AVX512DQ) are explicitly documented not needing to check for AVX512F if
>> the AVX512DQ bit is present.
> I think the "not" here is wrong? At least my copy (rev 024) requires
> all involved feature bits to be checked (see e.g. table 2-2 or the
> individual instruction pages).

Hmm - yet another inconsistency.  Some instructions specify a CPUID
dependency for just AVX512F (EVEX.NDS.512.66.0F.W1 C2 /r ib VCMPPD k1
{k2}, zmm2, zmm3/m512/m64bcst{sae}, imm8), some for AVX512F and a second
feature (EVEX.256.66.0F38.W1 19 /r VBROADCASTSD ymm1 {k1}{z}, xmm2/m64)
, and some only for the second feature (EVEX.512.66.0F.W0 79 /r
VCVTPS2UQQ zmm1 {k1}{z}, ymm2/m256/m32bcst{er})

FWIW, I still think the dependency expression is ok in its current form.

>
>> I think it wants to look something like:
>>
>> # AVX2 is an extension to AVX, providing mainly new integer instructions.
>> # In principle, AVX512 only depends on YMM register state, but many AVX2
> DYM ZMM register state here?

No.  AVX512 introduces ZMM registers.

To enable ZMM registers (and opmask) , YMM must be enabled in %xcr0, and
this is the dependency I am talking about.

~Andrew

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