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Re: [Xen-devel] [PATCH v2 09/20] arm/mm: Introduce modify_xen_mappings

Hi Konrad,

On 25/08/16 14:37, Konrad Rzeszutek Wilk wrote:
Which is only used by Livepatch code. The purpose behind
this call is to modify the page table entries flags.

Specifically the .ro and .nx flags. The current mechanism
puts cache attributes in the flags and the .ro and .nx are
locked down and assumed to be .ro=0, nx=1.

Livepatch needs .nx=0 and also .ro to be set to 1.

We introduce a new 'flags' where various bits determine
whether .ro and .nx bits are set or cleared. We can't use
an enum as the function prototype would diverge from x86.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>

Reviewed-by: Julien Grall <julien.grall@xxxxxxx>

with one minor request (see below).

diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h
index 05d9f82..2f66740 100644
--- a/xen/include/asm-arm/page.h
+++ b/xen/include/asm-arm/page.h
@@ -66,6 +66,17 @@

+ * Defines for changing the PTE .ro and .nx bits. This is only to be

I would say "hypervisor PTE" because the stage-2 page tables have different permission (read and write have separate bits).

+ * used with modify_xen_mappings.
+ */
+#define _PTE_NX_BIT     0U
+#define _PTE_RO_BIT     1U
+#define PTE_NX          (1U << _PTE_NX_BIT)
+#define PTE_RO          (1U << _PTE_RO_BIT)
+#define PTE_NX_MASK(x)  (((x) >> _PTE_NX_BIT) & 0x1U)
+#define PTE_RO_MASK(x)  (((x) >> _PTE_RO_BIT) & 0x1U)
  * Stage 2 Memory Type.
  * These are valid in the MemAttr[3:0] field of an LPAE stage 2 page


Julien Grall

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