Re: [Xen-devel] [PATCH v4 11/16] xen/arm32: Add an helper to invalidate all instruction caches

[Julien Grall <julien.grall@xxxxxxx>]

Hi Konrad,

On 16/09/2016 18:38, Konrad Rzeszutek Wilk wrote:
> This is exactly like commit fb9d877a9c0f3d4d15db8f6e0c5506ea641862c6
> "xen/arm64: Add an helper to invalidate all instruction caches"
> except it is on ARM32 side.
>
> When we are flushing the cache we are most likley also want
> to flush the branch predictor too. Hence we add this.
>
> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
>
> ---
> Cc: Julien Grall <julien.grall@xxxxxxx>
> Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>
>
> v2: First submission
> v3: Squashed "xen/arm32/livepatch: Add BPICALLIS to helper to invalidate
>     all instruction caches" in this patch.
> ---
>  xen/include/asm-arm/arm32/page.h | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
>
> diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h
> index bccdbfc..583ed75 100644
> --- a/xen/include/asm-arm/arm32/page.h
> +++ b/xen/include/asm-arm/arm32/page.h
> @@ -30,6 +30,19 @@ static inline void write_pte(lpae_t *p, lpae_t pte)
>  #define __clean_and_invalidate_dcache_one(R) STORE_CP32(R, DCCIMVAC)
>
>  /*
> + * Invalidate all instruction caches in Inner Shareable domain to PoU.
> + * We also need to flush the branch predictor for ARMv7 as it may be
> + * architecturally visible to the software (see B2.2.4 in ARM DDI 0406C.b).
> + */
> +static inline void invalidate_icache(void)
> +{
> +    asm volatile (
> +        CMD_CP32(ICIALLUIS)     /* Flush I-cache. */
> +        CMD_CP32(BPIALLIS)      /* Flush branch predictor. */
> +        : : : "memory");
This requires a dsb(ish); isb();

Which make me notice that I forgot to add this in the AArch64 
counterpart. I will send a patch later on.
> +}
> +
> +/*
>   * Flush all hypervisor mappings from the TLB and branch predictor of
>   * the local processor.
>   *
Regards,

--
Julien Grall

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