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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [ovmf baseline-only test] 67744: all pass
This run is configured for baseline tests only. flight 67744 ovmf real [real] http://osstest.xs.citrite.net/~osstest/testlogs/logs/67744/ Perfect :-) All tests in this flight passed as required version targeted for testing: ovmf 5919a9600e07b4700b54a5b47ae3991aad0e883c baseline version: ovmf 7419aedd93132f2dfc91e7bf3634fba7e0842c7b Last test of basis 67741 2016-09-21 20:18:01 Z 0 days Testing same since 67744 2016-09-22 06:47:21 Z 0 days 1 attempts ------------------------------------------------------------ People who touched revisions under test: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Feng Tian <feng.tian@xxxxxxxxx> Jeff Fan <jeff.fan@xxxxxxxxx> Jiewen Yao <jiewen.yao@xxxxxxxxx> Qin Long <qin.long@xxxxxxxxx> Star Zeng <star.zeng@xxxxxxxxx> jobs: build-amd64-xsm pass build-i386-xsm pass build-amd64 pass build-i386 pass build-amd64-libvirt pass build-i386-libvirt pass build-amd64-pvops pass build-i386-pvops pass test-amd64-amd64-xl-qemuu-ovmf-amd64 pass test-amd64-i386-xl-qemuu-ovmf-amd64 pass ------------------------------------------------------------ sg-report-flight on osstest.xs.citrite.net logs: /home/osstest/logs images: /home/osstest/images Logs, config files, etc. are available at http://osstest.xs.citrite.net/~osstest/testlogs/logs Test harness code can be found at http://xenbits.xensource.com/gitweb?p=osstest.git;a=summary Push not applicable. ------------------------------------------------------------ commit 5919a9600e07b4700b54a5b47ae3991aad0e883c Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Wed Sep 14 16:54:50 2016 +0800 SecurityPkg/TPM2: Sync PcrAllocations and PcrMask Current TCG2 implementation will set Tpm2HashMask PCD value according to TPM2 PCR bank. However, there might be misconfiguration in BIOS build phase. The enhanced logic makes sure that the current PCR allocations, the TPM supported PCRs, and the PcdTpm2HashMask are all in agreement. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit 07cdba18cd974d818556d752facfbf35a8d0f012 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Wed Sep 14 16:28:12 2016 +0800 SecurityPkg/TPM2: Extract GetSupportedAndActivePcrs to Tpm2CommandLib This patch extracts function Tpm2GetCapabilitySupportedAndActivePcrs() from drivers and also update Tcg2ExecutePhysicalPresence() to call Tpm2GetCapabilitySupportedAndActivePcrs() instead of Tcg2Protocol->GetCapability to query the TPM to determine which hashing algorithms are supported. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit f5e34e37e018034bc8ce7a2fb9ecb176d948b143 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Wed Sep 14 10:45:19 2016 +0800 SecurityPkg/TPM2: Move CopyDigestListToBuffer() to Tpm2CommandLib This patch just moves function CopyDigestListToBuffer() from drivers to library with HashAlgorithmMask parameter added to make the interface more applicable. The related function IsHashAlgSupportedInHashAlgorithmMask() is also moved from drivers to library as internal function. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit 77e55cf4e283942766d6178eca375aeec055bff2 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Wed Sep 14 10:07:45 2016 +0800 SecurityPkg/TPM2: Move GetDigestListSize() to Tpm2CommandLib This patch just moves function GetDigestListSize() from drivers to library and no functionality change. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit f28ab8494664411ac9b3ec22b82d714d8a3ca4c1 Author: Star Zeng <star.zeng@xxxxxxxxx> Date: Tue Sep 13 19:12:07 2016 +0800 SecurityPkg/TPM2: Update function header of GetDigestFromDigestList() Update the return status description and use OUT identifier instead of IN for Digest parameter, no functionality change. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Cc: Jiewen Yao <jiewen.yao@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit d4b9b2c32cb38c8aefed52de12368ba644dfb0b5 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Tue Sep 13 19:05:08 2016 +0800 SecurityPkg/TPM2: Move GetDigestFromDigestList() to Tpm2CommandLib This patch just moves function Tpm2GetDigestFromDigestList() from drivers to library as GetDigestFromDigestList() and no functionality change. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit f9c9a1406c7393f01961fbc07f6b6f47ce7f4137 Author: Jiewen Yao <jiewen.yao@xxxxxxxxx> Date: Tue Sep 13 18:43:30 2016 +0800 SecurityPkg/TPM2: Move Tpm2PcrAllocateBanks() to Tpm2CommandLib This patch just moves function Tpm2CommandAllocPcr() from DxeTcg2PhysicalPresenceLib.c to Tpm2CommandLib as Tpm2PcrAllocateBanks() and no functionality change. Cc: Chao B Zhang <chao.b.zhang@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@xxxxxxxxx> Signed-off-by: Star Zeng <star.zeng@xxxxxxxxx> Reviewed-by: Chao Zhang <chao.b.zhang@xxxxxxxxx> commit 558311c94a7eb5ab2108698800498d074572555c Author: Qin Long <qin.long@xxxxxxxxx> Date: Wed Sep 21 10:17:01 2016 +0800 CryptoPkg: Clean up unreferenced symbol in Cryptest utility. Remove "TSCounterSignature" from TSVerify.c, which is not being used by anyone. Cc: Ting Ye <ting.ye@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Qin Long <qin.long@xxxxxxxxx> Reviewed-by: Ting Ye <ting.ye@xxxxxxxxx> commit 493b40451d4f841c14f9ee35da1492084baa8d9b Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Tue Sep 13 18:25:14 2016 +0100 ArmPkg/AsmMacroIoLib: force word alignment for functions Without an explicit .align directive, the Clang assembler defaults to no alignment, which may result in instructions appearing misaligned in the final executable. So use word alignment in all cases. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> commit 3c3cf1cd731f5aa8fdc00392cbf7c5e36055bf18 Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Tue Sep 13 16:36:23 2016 +0100 ArmVirtPkg: move all platforms to MdePkg/ BaseMemoryLib implementations The BaseMemoryLibStm implementation under ArmPkg/ is being deprecated, in favor of the generic versions under MdePkg, now that ARM and AARCH64 support has been added to both the generic C version (BaseMemoryLib) and the accelerated version (BaseMemoryLibOptDxe). The latter uses unaligned accesses and special cache maintenance instructions, and can therefore not be used when the MMU is off. So move to BaseMemoryLibOptDxe for the DXE phase and later, and to the generic BaseMemoryLib before that. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Laszlo Ersek <lersek@xxxxxxxxxx> commit 217b3ac093d2c1ae2ce066984a9c4302331c07c2 Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Fri Sep 16 11:25:52 2016 +0100 MdePkg/BaseMemoryLibOptDxe ARM|AARCH64: implement accelerated GUID functions As reported by Vishal, CompareGuid() is a hotspot, and switching from BaseMemoryLibStm in ArmPkg/ to BaseMemoryLibOptDxe causes a noticeable performance regression due to the fact that BaseMemoryLibOptDxe uses unaligned accessors explicitly to implement CompareGuid() and the related functions. Since BaseMemoryLibOptDxe on ARM and AARCH64 can only be used in contexts where unaligned accesses are allowed, reimplement these functions for ARM and AARCH64 specifically, using wide accessors that can tolerate any misalignment. Reported-by: "Oliyil Kunnil, Vishal" <vishalo@xxxxxxxxxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit 60fe5e8a9c8deafcc302c715a91947d75d38e544 Author: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Date: Tue Sep 13 18:22:33 2016 +0100 MdePkg/BaseMemoryLibOptDxe ARM: fix arithmetic bugs in CompareMem() Fix two bugs: - Erroneous shift of 2 in a bytes to bits conversion. - Use reverse subtract rather than negate for value that is subsequently used as operand #2 in a shift operation. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@xxxxxxxxxx> Reviewed-by: Liming Gao <liming.gao@xxxxxxxxx> commit 93638568c1c6bd6bace2cd27666796b7c87fc45c Author: Jeff Fan <jeff.fan@xxxxxxxxx> Date: Tue Sep 20 16:17:26 2016 +0800 UefiCpuPkg/SecCore: SecPlatformInformation(2) are optional PPIs Currently, this is ASSERT() if neither SecPlatformInformation2 nor SecPlatformInformation PPIs are found. This is not correct. Per PI specification both of them are optional PPI. Platform may not install them. Cc: Michael Kinney <michael.d.kinney@xxxxxxxxx> Cc: Feng Tian <feng.tian@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@xxxxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> commit 030d2de7c7a8682837be168bbaf7f27739a8fff0 Author: Jeff Fan <jeff.fan@xxxxxxxxx> Date: Tue Sep 20 16:08:28 2016 +0800 UefiCpuPkg/SecCore: Fix comment typo Revert SecPlatformInformation2 and SecPlatformInformation in two comment blocks. And correct the words. Cc: Michael Kinney <michael.d.kinney@xxxxxxxxx> Cc: Feng Tian <feng.tian@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@xxxxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> commit 26ea0da235fe4082ef338f37d7ac292ce259c586 Author: Jeff Fan <jeff.fan@xxxxxxxxx> Date: Tue Sep 20 16:03:18 2016 +0800 QuarkPlatformPkg/PlatformSecLib: Fix stack pointer issue in Flat32.S ESP should be set to top of eSRAM range that aligns with Flat32.asm. Because CPU BIST data will be located at top of STACK, this issue leads Platform Sec Lib cannot get the correct CPU BIST information. This fix is to address below issue: https://tianocore.acgmultimedia.com/show_bug.cgi?id=123 Cc: Steven Shi <Steven.shi@xxxxxxxxx> Cc: Michael Kinney <michael.d.kinney@xxxxxxxxx> Cc: Kelly Steele <kelly.steele@xxxxxxxxx> Cc: Feng Tian <feng.tian@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@xxxxxxxxx> Reviewed-by: Michael Kinney <michael.d.kinney@xxxxxxxxx> commit 1f87985ab7958664a84da78095b5892f88acf3f1 Author: Feng Tian <feng.tian@xxxxxxxxx> Date: Wed Sep 14 09:48:40 2016 +0800 MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng <star.zeng@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> commit dbe10619bc443215477c5c0c4c949410bf68b1ec Author: Feng Tian <feng.tian@xxxxxxxxx> Date: Wed Sep 14 09:36:11 2016 +0800 MdeModulePkg/XhciDxe:1ms delay before access MMIO reg during reset Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during HC reset. As this delay is not defined by XHCI spec, we use this workaround to fix the issue. Cc: Star Zeng <star.zeng@xxxxxxxxx> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@xxxxxxxxx> Reviewed-by: Star Zeng <star.zeng@xxxxxxxxx> _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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