Re: [Xen-devel] [PATCH v3 01/15] docs: L2 Cache Allocation Technology (CAT) feature document.

[Yi Sun <yi.y.sun@xxxxxxxxxxxxxxx>]

On 16-11-11 16:33:09, Konrad Rzeszutek Wilk wrote:
> On Tue, Oct 25, 2016 at 11:40:49AM +0800, Yi Sun wrote:
> > Signed-off-by: Yi Sun <yi.y.sun@xxxxxxxxxxxxxxx>
> > ---
> >  docs/features/l2_cat.pandoc | 314 
> > ++++++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 314 insertions(+)
> >  create mode 100644 docs/features/l2_cat.pandoc
> > 
> > +# Overview
> > +
> > +L2 CAT allows an OS or Hypervisor/VMM to control allocation of a
> 
> Could you define CAT?
> 
Sure, thanks!

> > +# Technical information
> > +
> > +L2 CAT is a member of Intel PSR features and part of CAT, it shares
> 
> Could you define 'PSR' here? Usually when you introduce an acronym
> you do something like:
> 
> Intel Problem Solver Resolver (PSR)
> 
> and that makes it easy for folks to map the acronym to the full feature.
> 
Thanks for tips!

> > +## The relationship between L2 CAT and L3 CAT/CDP
> > +
> > +L2 CAT is independent of L3 CAT/CDP, which means L2 CAT would be enabled
> 
> Could you define CDP?
> 
Sure, thanks!

> > +N.B. L2 CAT and L3 CAT/CDP share the same COS field in the same
> > +associate register `IA32_PQR_ASSOC`, which means one COS associate to a
> 
> s/COS associate/COS associate's/ ?
> 
Thanks!

> > +COS 9 would be enforced, but for L2 CAT, the behavior is fully open (no
> > +limit) since COS 9 is beyond the max COS (8) of L2 CAT.
> 
> Thanks for the explanation.
> 
> 
> ..snip..
> [didnt' have any questions below]
Thanks a lot for review!

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