[Xen-devel] [PATCH 13/13] xen/arm: vgic-v3: Allow AArch32 guest booting with GICv3

[Julien Grall <julien.grall@xxxxxxx>]

AArch32 guest will use co-processor registers to access the GICv3 (see
8.5 in IHI 0069C). Some of the registers have to be trapped and emulated
(e.g ICC_SGI1R), this is the purpose of this patch.

The rest of the emulation already supports access required for AArch32
so nothing has to be changed there.

Note this is only enabling 32-bit guest using GICv3 on Xen ARM64. Further
work would be required to compile GICv3 and vGICv3 for Xen ARM32.

Signed-off-by: Julien Grall <julien.grall@xxxxxxx>
---
 xen/arch/arm/traps.c             | 12 ++++++++++++
 xen/arch/arm/vgic-v3.c           | 20 ++++++++++++++++++++
 xen/include/asm-arm/cpregs.h     |  3 +++
 xen/include/asm-arm/perfc_defn.h |  2 ++
 4 files changed, 37 insertions(+)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 1fe02cb..eb85d92 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1876,6 +1876,18 @@ static void do_cp15_64(struct cpu_user_regs *regs,
         break;
 
     /*
+     * HCR_EL2.FMO or HCR_EL2.IMO
+     *
+     * GIC Architecture Specification (IHI 0069C): Section 4.6.3
+     */
+    case HSR_CPREG64(ICC_SGI1R):
+    case HSR_CPREG64(ICC_ASGI1R):
+    case HSR_CPREG64(ICC_SGI0R):
+        if ( !vgic_emulate(regs, hsr) )
+            return inject_undef_exception(regs, hsr);
+        break;
+
+    /*
      * CPTR_EL2.T{0..9,12..13}
      *
      * ARMv7 (DDI 0406C.b): B1.14.12
diff --git a/xen/arch/arm/vgic-v3.c b/xen/arch/arm/vgic-v3.c
index f23135d..22c8ce0 100644
--- a/xen/arch/arm/vgic-v3.c
+++ b/xen/arch/arm/vgic-v3.c
@@ -1335,12 +1335,32 @@ static bool vgic_v3_emulate_sysreg(struct cpu_user_regs 
*regs, union hsr hsr)
     }
 }
 
+static bool vgic_v3_emulate_cp64(struct cpu_user_regs *regs, union hsr hsr)
+{
+    struct hsr_cp64 cp64 = hsr.cp64;
+
+    if ( cp64.read )
+        perfc_incr(vgic_cp64_reads);
+    else
+        perfc_incr(vgic_cp64_writes);
+
+    switch ( hsr.bits & HSR_CP64_REGS_MASK )
+    {
+    case HSR_CPREG64(ICC_SGI1R):
+        return vreg_emulate_cp64(regs, hsr, vgic_v3_emulate_sgi1r);
+    default:
+        return false;
+    }
+}
+
 static bool vgic_v3_emulate_reg(struct cpu_user_regs *regs, union hsr hsr)
 {
     switch (hsr.ec)
     {
     case HSR_EC_SYSREG:
         return vgic_v3_emulate_sysreg(regs, hsr);
+    case HSR_EC_CP15_64:
+        return vgic_v3_emulate_cp64(regs, hsr);
     default:
         return false;
     }
diff --git a/xen/include/asm-arm/cpregs.h b/xen/include/asm-arm/cpregs.h
index e5cb00c..af45ec7 100644
--- a/xen/include/asm-arm/cpregs.h
+++ b/xen/include/asm-arm/cpregs.h
@@ -246,6 +246,9 @@
 /* CP15 CR11: DMA Operations for TCM Access */
 
 /* CP15 CR12:  */
+#define ICC_SGI1R       p15,0,c12       /* Interrupt Controller SGI Group 1 */
+#define ICC_ASGI1R      p15,1,c12       /* Interrupt Controller Alias SGI 
Group 1 Register */
+#define ICC_SGI0R       p15,2,c12       /* Interrupt Controller SGI Group 0 */
 #define VBAR            p15,0,c12,c0,0  /* Vector Base Address Register */
 #define HVBAR           p15,4,c12,c0,0  /* Hyp. Vector Base Address Register */
 
diff --git a/xen/include/asm-arm/perfc_defn.h b/xen/include/asm-arm/perfc_defn.h
index 69fabe7..5f957ee 100644
--- a/xen/include/asm-arm/perfc_defn.h
+++ b/xen/include/asm-arm/perfc_defn.h
@@ -38,6 +38,8 @@ PERFCOUNTER(vgicd_reads,                "vgicd: read")
 PERFCOUNTER(vgicd_writes,               "vgicd: write")
 PERFCOUNTER(vgicr_reads,                "vgicr: read")
 PERFCOUNTER(vgicr_writes,               "vgicr: write")
+PERFCOUNTER(vgic_cp64_reads,            "vgic: cp64 read")
+PERFCOUNTER(vgic_cp64_writes,           "vgic: cp64 write")
 PERFCOUNTER(vgic_sysreg_reads,          "vgic: sysreg read")
 PERFCOUNTER(vgic_sysreg_writes,         "vgic: sysreg write")
 PERFCOUNTER(vgic_sgi_list  ,            "vgic: SGI send to list")
-- 
1.9.1


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