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Re: [Xen-devel] [RFC PATCH v2 05/26] ARM: GICv3 ITS: introduce ITS command handling



On Thu, 22 Dec 2016, Andre Przywara wrote:
> To be able to easily send commands to the ITS, create the respective
> wrapper functions, which take care of the ring buffer.
> The first two commands we implement provide methods to map a collection
> to a redistributor (aka host core) and to flush the command queue (SYNC).
> Start using these commands for mapping one collection to each host CPU.
> 
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>

Hi Andre,

please address Julien's comments too


> ---
>  xen/arch/arm/gic-its.c        | 100 
> ++++++++++++++++++++++++++++++++++++++++++
>  xen/arch/arm/gic-v3.c         |  15 +++++++
>  xen/include/asm-arm/gic-its.h |  33 ++++++++++++++
>  3 files changed, 148 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-its.c b/xen/arch/arm/gic-its.c
> index 2fb3bcb..d0f5fd1 100644
> --- a/xen/arch/arm/gic-its.c
> +++ b/xen/arch/arm/gic-its.c
> @@ -34,6 +34,10 @@ static struct {
>      unsigned int host_lpi_bits;
>  } lpi_data;
>  
> +/* Physical redistributor address */
> +static DEFINE_PER_CPU(uint64_t, rdist_addr);
> +/* Redistributor ID */
> +static DEFINE_PER_CPU(uint64_t, rdist_id);
>  /* Pending table for each redistributor */
>  static DEFINE_PER_CPU(void *, pending_table);
>  
> @@ -41,6 +45,85 @@ static DEFINE_PER_CPU(void *, pending_table);
>  
>  #define ITS_CMD_QUEUE_SZ                                SZ_64K
>  
> +static int its_send_command(struct host_its *hw_its, void *its_cmd)
> +{
> +    uint64_t readp, writep;
> +
> +    spin_lock(&hw_its->cmd_lock);
> +
> +    readp = readq_relaxed(hw_its->its_base + GITS_CREADR) & GENMASK(19, 5);
> +    writep = readq_relaxed(hw_its->its_base + GITS_CWRITER) & GENMASK(19, 5);
> +
> +    if ( ((writep + ITS_CMD_SIZE) % ITS_CMD_QUEUE_SZ) == readp )
> +    {
> +        spin_unlock(&hw_its->cmd_lock);
> +        return -EBUSY;
> +    }
> +
> +    memcpy(hw_its->cmd_buf + writep, its_cmd, ITS_CMD_SIZE);
> +    __flush_dcache_area(hw_its->cmd_buf + writep, ITS_CMD_SIZE);
> +    writep = (writep + ITS_CMD_SIZE) % ITS_CMD_QUEUE_SZ;
> +
> +    writeq_relaxed(writep & GENMASK(19, 5), hw_its->its_base + GITS_CWRITER);
> +
> +    spin_unlock(&hw_its->cmd_lock);
> +
> +    return 0;
> +}
> +
> +static uint64_t encode_rdbase(struct host_its *hw_its, int cpu, uint64_t reg)
> +{
> +    reg &= ~GENMASK(51, 16);
> +
> +    if ( hw_its->pta )
> +        reg |= per_cpu(rdist_addr, cpu) & GENMASK(51, 16);
> +    else
> +        reg |= per_cpu(rdist_id, cpu) << 16;
> +
> +    return reg;
> +}
> +
> +static int its_send_cmd_sync(struct host_its *its, int cpu)
> +{
> +    uint64_t cmd[4];
> +
> +    cmd[0] = GITS_CMD_SYNC;
> +    cmd[1] = 0x00;
> +    cmd[2] = encode_rdbase(its, cpu, 0x0);
> +    cmd[3] = 0x00;
> +
> +    return its_send_command(its, cmd);
> +}
> +
> +static int its_send_cmd_mapc(struct host_its *its, int collection_id, int 
> cpu)
> +{
> +    uint64_t cmd[4];
> +
> +    cmd[0] = GITS_CMD_MAPC;
> +    cmd[1] = 0x00;
> +    cmd[2] = encode_rdbase(its, cpu, (collection_id & GENMASK(15, 0)));
> +    cmd[2] |= BIT_ULL(63);
> +    cmd[3] = 0x00;
> +
> +    return its_send_command(its, cmd);
> +}
> +
> +/* Set up the (1:1) collection mapping for the given host CPU. */
> +void gicv3_its_setup_collection(int cpu)
> +{
> +    struct host_its *its;
> +
> +    list_for_each_entry(its, &host_its_list, entry)
> +    {
> +        /* Only send commands to ITS that have been initialized already. */
> +        if ( !its->cmd_buf )
> +            continue;

Please add a comment to say that this function gets called on cpu0 when
ITS is not initialized, this is why the check is necessary.


> +        its_send_cmd_mapc(its, cpu, cpu);
> +        its_send_cmd_sync(its, cpu);

We need to check for returned errors


> +    }
> +}
> +
>  #define BASER_ATTR_MASK                                           \
>          ((0x3UL << GITS_BASER_SHAREABILITY_SHIFT)               | \
>           (0x7UL << GITS_BASER_OUTER_CACHEABILITY_SHIFT)         | \
> @@ -148,6 +231,13 @@ int gicv3_its_init(struct host_its *hw_its)
>      if ( !hw_its->its_base )
>          return -ENOMEM;
>  
> +    /* Make sure the ITS is disabled before programming the BASE registers. 
> */
> +    reg = readl_relaxed(hw_its->its_base + GITS_CTLR);
> +    writel_relaxed(reg & ~GITS_CTLR_ENABLE, hw_its->its_base + GITS_CTLR);
> +
> +    reg = readq_relaxed(hw_its->its_base + GITS_TYPER);
> +    hw_its->pta = !!(reg & GITS_TYPER_PTA);
> +
>      for ( i = 0; i < GITS_BASER_NR_REGS; i++ )
>      {
>          void __iomem *basereg = hw_its->its_base + GITS_BASER0 + i * 8;
> @@ -175,9 +265,18 @@ int gicv3_its_init(struct host_its *hw_its)
>      if ( !hw_its->cmd_buf )
>          return -ENOMEM;
>  
> +    its_send_cmd_mapc(hw_its, smp_processor_id(), smp_processor_id());
> +    its_send_cmd_sync(hw_its, smp_processor_id());

We need to check for returned errors.

Please add a comment to say that we are collection mapping cpu0. Also,
it could be done by calling gicv3_its_setup_collection.


>      return 0;
>  }
>  
> +void gicv3_set_redist_addr(paddr_t address, int redist_id)
> +{
> +    this_cpu(rdist_addr) = address;
> +    this_cpu(rdist_id) = redist_id;
> +}
> +
>  uint64_t gicv3_lpi_allocate_pendtable(void)
>  {
>      uint64_t reg, attr;
> @@ -286,6 +385,7 @@ void gicv3_its_dt_init(const struct dt_device_node *node)
>          its_data->addr = addr;
>          its_data->size = size;
>          its_data->dt_node = its;
> +        spin_lock_init(&its_data->cmd_lock);
>  
>          printk("GICv3: Found ITS @0x%lx\n", addr);
>  
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 8ca7da2..d2461cb 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -643,6 +643,8 @@ static int gicv3_rdist_init_lpis(void __iomem * 
> rdist_base)
>          return -ENOMEM;
>      writeq_relaxed(table_reg, rdist_base + GICR_PROPBASER);
>  
> +    gicv3_its_setup_collection(smp_processor_id());
> +
>      return 0;
>  }
>  
> @@ -691,8 +693,21 @@ static int __init gicv3_populate_rdist(void)
>  
>                  if ( typer & GICR_TYPER_PLPIS )
>                  {
> +                    paddr_t rdist_addr;
>                      int ret;
>  
> +                    rdist_addr = gicv3.rdist_regions[i].base;
> +                    rdist_addr += ptr - gicv3.rdist_regions[i].map_base;
> +
> +                    /* The ITS refers to redistributors either by their 
> physical
> +                     * address or by their ID. Determine those two values and
> +                     * let the ITS code store them in per host CPU variables 
> to
> +                     * later be able to address those redistributors.
> +                     */
> +                    gicv3_set_redist_addr(rdist_addr,
> +                                          (typer >> GITS_TYPER_IDBITS_SHIFT) 
> &
> +                                          GENMASK(15, 0));
> +
>                      ret = gicv3_rdist_init_lpis(ptr);
>                      if ( ret && ret != -ENODEV )
>                      {
> diff --git a/xen/include/asm-arm/gic-its.h b/xen/include/asm-arm/gic-its.h
> index e0fded8..68e5f63 100644
> --- a/xen/include/asm-arm/gic-its.h
> +++ b/xen/include/asm-arm/gic-its.h
> @@ -38,6 +38,8 @@
>  
>  /* Register bits */
>  #define GITS_CTLR_ENABLE                BIT_ULL(0)
> +#define GITS_TYPER_PTA                  BIT_ULL(19)
> +#define GITS_TYPER_IDBITS_SHIFT         8
>  #define GITS_IIDR_VALUE                 0x34c
>  
>  #define GITS_BASER_VALID                BIT_ULL(63)
> @@ -63,6 +65,22 @@
>  
>  #define GITS_CBASER_SIZE_MASK           0xff
>  
> +/* ITS command definitions */
> +#define ITS_CMD_SIZE                    32
> +
> +#define GITS_CMD_MOVI                   0x01
> +#define GITS_CMD_INT                    0x03
> +#define GITS_CMD_CLEAR                  0x04
> +#define GITS_CMD_SYNC                   0x05
> +#define GITS_CMD_MAPD                   0x08
> +#define GITS_CMD_MAPC                   0x09
> +#define GITS_CMD_MAPTI                  0x0a
> +#define GITS_CMD_MAPI                   0x0b
> +#define GITS_CMD_INV                    0x0c
> +#define GITS_CMD_INVALL                 0x0d
> +#define GITS_CMD_MOVALL                 0x0e
> +#define GITS_CMD_DISCARD                0x0f
> +
>  #ifndef __ASSEMBLY__
>  #include <xen/device_tree.h>
>  
> @@ -73,7 +91,9 @@ struct host_its {
>      paddr_t addr;
>      paddr_t size;
>      void __iomem *its_base;
> +    spinlock_t cmd_lock;
>      void *cmd_buf;
> +    bool pta;
>  };
>  
>  extern struct list_head host_its_list;
> @@ -93,6 +113,12 @@ uint64_t gicv3_lpi_allocate_pendtable(void);
>  int gicv3_lpi_init_host_lpis(unsigned int nr_lpis);
>  int gicv3_its_init(struct host_its *hw_its);
>  
> +/* Set the physical address and ID for each redistributor as read from DT. */
> +void gicv3_set_redist_addr(paddr_t address, int redist_id);
> +
> +/* Map a collection for this host CPU to each host ITS. */
> +void gicv3_its_setup_collection(int cpu);
> +
>  #else
>  
>  static inline void gicv3_its_dt_init(const struct dt_device_node *node)
> @@ -114,6 +140,13 @@ static inline int gicv3_its_init(struct host_its *hw_its)
>  {
>      return 0;
>  }
> +static inline void gicv3_set_redist_addr(paddr_t address, int redist_id)
> +{
> +}
> +static inline void gicv3_its_setup_collection(int cpu)
> +{
> +}
> +
>  #endif /* CONFIG_HAS_ITS */
>  
>  #endif /* __ASSEMBLY__ */
> -- 
> 2.9.0
> 

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