[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] IOMMU fault with IGD passthrough setup on XEN 4.8.0
>>> On 16.01.17 at 16:21, <firemeteor@xxxxxxxxxxxxxxxxxxxxx> wrote: > BTW, before I generate more verbose && complete debug log, just want to > update that I also see the following in dom0 (without attempting any > pass-through to the IGD device) > But this time the log is not flooding at all. Not sure if this is relevant > to what I see from the domU with pci pass-through. > > (XEN) Bogus DMIBAR 0xfed18001 on 0000:00:00.0 > (XEN) [VT-D]DMAR:[DMA Write] Request device [0000:00:02.0] fault addr > 7300000000, iommu reg = ffff82c000201000 > (XEN) [VT-D]DMAR: reason 05 - PTE Write access is not set > (XEN) [VT-D]DMAR:[DMA Write] Request device [0000:00:02.0] fault addr > 7300000000, iommu reg = ffff82c000201000 > (XEN) [VT-D]DMAR: reason 05 - PTE Write access is not set > (XEN) [VT-D]DMAR:[DMA Write] Request device [0000:00:02.0] fault addr > 7300000000, iommu reg = ffff82c000201000 > (XEN) [VT-D]DMAR: reason 05 - PTE Write access is not set > (XEN) [VT-D]DMAR:[DMA Write] Request device [0000:00:02.0] fault addr > 7300000000, iommu reg = ffff82c000201000 > (XEN) [VT-D]DMAR: reason 05 - PTE Write access is not set > (XEN) [VT-D]DMAR:[DMA Write] Request device [0000:00:02.0] fault addr > 7300000000, iommu reg = ffff82c000201000 > (XEN) [VT-D]DMAR: reason 05 - PTE Write access is not set This address is clearly neither RAM nor covered by any RMRR, so the question is why there is I/O being generated to it. Is it perhaps named by one of the device's BARs? Jan _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
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