Re: [Xen-devel] [PATCH] xen/arm: gic-v3: Make sure read from ICC_IAR1_EL1 is visible on the redistributor

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Wed, 18 Jan 2017, Julien Grall wrote:
> >From the GICv3 spec (IHI069C) section 4.1.1:
> "The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a
> returned INTID are not guaranteed to be visible until after the execution
> of a DSB".
> 
> Because of the GIC is an external component, a dsb sy is required.
> Without it the sysreg read may not have been made visible on the
> redistributor.
> 
> Signed-off-by: Julien Grall <julien.grall@xxxxxxx>

Reviewed-by: Stefano Stabellini <sstabellini@xxxxxxxxxx>

> ---
> 
> This patch should be backported up to Xen 4.6.
> ---
>  xen/arch/arm/gic-v3.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c
> index 57ed9d9..955591b 100644
> --- a/xen/arch/arm/gic-v3.c
> +++ b/xen/arch/arm/gic-v3.c
> @@ -459,7 +459,11 @@ static void gicv3_dir_irq(struct irq_desc *irqd)
>  
>  static unsigned int gicv3_read_irq(void)
>  {
> -    return READ_SYSREG32(ICC_IAR1_EL1);
> +    unsigned int irq = READ_SYSREG32(ICC_IAR1_EL1);
> +
> +    dsb(sy);
> +
> +    return irq;
>  }
>  
>  static inline uint64_t gicv3_mpidr_to_affinity(int cpu)
> -- 
> 1.9.1
> 

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