[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [Xen-devel] [PATCH 0/8] x86emul: MMX/SSE/SSE2 support
This includes support for AVX counterparts of them as well as a few later SSE additions (basically covering the entire 0f-prefixed opcode space, but not the 0f38 and 0f3a ones, nor 3dnow). This series is still partly RFC, as I've still not worked out a good way of testing the new additions - for now I've only kept individual insn tests which I had prepared for earlier (rejected) patch submissions. 1: catch exceptions occurring in stubs 2: support most memory accessing MMX/SSE/SSE2 insns 3: support MMX/SSE/SSE2 moves 4: support MMX/SSE/SSE2 converts 5: support {,V}{,U}COMIS{S,D} 6: support MMX/SSE/SSE2 insns with only register operands 7: support {,V}{LD,ST}MXCSR 8: support {,V}MOVNTDQA Signed-off-by: Jan Beulich <jbeulich@xxxxxxxx> _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxx https://lists.xen.org/xen-devel
|
Lists.xenproject.org is hosted with RackSpace, monitoring our |