Re: [Xen-devel] [PATCH 05/28] ARM: GICv3 ITS: map ITS command buffer

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

On Mon, 30 Jan 2017, Andre Przywara wrote:
> Instead of directly manipulating the tables in memory, an ITS driver
> sends commands via a ring buffer to the ITS h/w to create or alter the
> LPI mappings.
> Allocate memory for that buffer and tell the ITS about it to be able
> to send ITS commands.
> 
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> ---
>  xen/arch/arm/gic-v3-its.c        | 46 
> ++++++++++++++++++++++++++++++++++++++++
>  xen/include/asm-arm/gic_v3_its.h |  6 ++++++
>  2 files changed, 52 insertions(+)
> 
> diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c
> index c31fef6..ad7cd2a 100644
> --- a/xen/arch/arm/gic-v3-its.c
> +++ b/xen/arch/arm/gic-v3-its.c
> @@ -27,6 +27,8 @@
>  #include <asm/gic_v3_its.h>
>  #include <asm/io.h>
>  
> +#define ITS_CMD_QUEUE_SZ                SZ_64K
> +
>  #define BASER_ATTR_MASK                                           \
>          ((0x3UL << GITS_BASER_SHAREABILITY_SHIFT)               | \
>           (0x7UL << GITS_BASER_OUTER_CACHEABILITY_SHIFT)         | \
> @@ -44,6 +46,45 @@ static uint64_t encode_phys_addr(paddr_t addr, int 
> page_bits)
>      return ret | (addr & GENMASK(51, 48)) >> (48 - 12);
>  }
>  
> +static void *its_map_cbaser(struct host_its *its)
> +{
> +    void __iomem *cbasereg = its->its_base + GITS_CBASER;
> +    uint64_t reg, regc;
> +    void *buffer;
> +    paddr_t paddr;
> +
> +    reg  = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT;
> +    reg |= GIC_BASER_CACHE_SameAsInner << 
> GITS_BASER_OUTER_CACHEABILITY_SHIFT;
> +    reg |= GIC_BASER_CACHE_RaWaWb << GITS_BASER_INNER_CACHEABILITY_SHIFT;
> +
> +    buffer = _xzalloc(ITS_CMD_QUEUE_SZ, PAGE_SIZE);
> +    if ( !buffer )
> +        return NULL;
> +    paddr = virt_to_maddr(buffer);
> +    ASSERT(!(paddr & ~GENMASK(51, 12)));
> +
> +    reg |= GITS_VALID_BIT | paddr;
> +    reg |= ((ITS_CMD_QUEUE_SZ / PAGE_SIZE) - 1) & GITS_CBASER_SIZE_MASK;
> +    writeq_relaxed(reg, cbasereg);
> +    regc = readq_relaxed(cbasereg);
> +
> +    /* If the ITS dropped shareability, drop cacheability as well. */
> +    if ( (regc & GITS_BASER_SHAREABILITY_MASK) == 0 )
> +    {
> +        regc &= ~GITS_BASER_INNER_CACHEABILITY_MASK;
> +        writeq_relaxed(regc, cbasereg);
> +    }
> +
> +    /*
> +     * If the command queue memory is mapped as uncached, we need to flush
> +     * it on every access.
> +     */
> +    if ( !(regc & GITS_BASER_INNER_CACHEABILITY_MASK) )
> +        its->flags |= HOST_ITS_FLUSH_CMD_QUEUE;
> +
> +    return buffer;
> +}
> +
>  #define PAGE_BITS(sz) ((sz) * 2 + PAGE_SHIFT)
>  
>  static int its_map_baser(void __iomem *basereg, uint64_t regc, int nr_items)
> @@ -150,6 +191,11 @@ int gicv3_its_init(struct host_its *hw_its)
>          }
>      }
>  
> +    hw_its->cmd_buf = its_map_cbaser(hw_its);
> +    if ( !hw_its->cmd_buf )
> +        return -ENOMEM;
> +    writeq_relaxed(0, hw_its->its_base + GITS_CWRITER);
 
Why this new write?

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